Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

53 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 96
54 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 97
55 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 98
56 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 99
57 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 100
58 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 100
59 MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 101
60 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 101
61 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...................... 102
62 Receive Unicast Enable Set Register (RXUNICASTSET) .......................................................... 105
63 Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 106
64 Receive Maximum Length Register (RXMAXLEN) ................................................................... 107
65 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 107
66 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 108
67 Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH) ..................................... 108
68 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) ............................................ 109
69 MAC Control Register (MACCONTROL) .............................................................................. 110
70 MAC Status Register (MACSTATUS) .................................................................................. 112
71 Emulation Control Register (EMCONTROL) .......................................................................... 114
72 FIFO Control Register (FIFOCONTROL) .............................................................................. 114
73 MAC Configuration Register (MACCONFIG) ......................................................................... 115
74 Soft Reset Register (SOFTRESET) .................................................................................... 115
75 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 116
76 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 116
77 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 117
78 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 117
79 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 118
80 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 118
81 Receive Pause Timer Register (RXPAUSE) .......................................................................... 119
82 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 119
83 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 120
84 MAC Address High Bytes Register (MACADDRHI) .................................................................. 121
85 MAC Index Register (MACINDEX) ..................................................................................... 121
86 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) .......................................... 122
87 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) .......................................... 122
88 Transmit Channel n Completion Pointer Register (TX nCP) ......................................................... 123
89 Receive Channel n Completion Pointer Register (RX nCP) ......................................................... 123
90 Statistics Register ......................................................................................................... 124
SPRUEQ6 – December 2007 List of Figures 7
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