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Dead-Band Submodule Registers
Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions
Bits Name Value Description
15-6 Reserved Reserved
5-4 IN_MODE Dead Band Input Mode Control
Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28 .
This allows you to select the input source to the falling-edge and rising-edge delay.
To produce classical dead-band waveforms the default is EPWMxA In is the source for both
falling and rising-edge delays.
00 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge
delay.
01 EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
10 EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
11 EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and
falling-edge delayed signal.
3-2 POLSEL Polarity Select Control
Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 2-28 .
This allows you to selectively invert one of the delayed signals before it is sent out of the
dead-band submodule.
The following descriptions correspond to classical upper/lower switch control as found in one
leg of a digital motor control inverter.
These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other
enhanced modes are also possible, but not regarded as typical usage modes.
00 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
01 Active low complementary (ALC) mode. EPWMxA is inverted.
10 Active high complementary (AHC). EPWMxB is inverted.
11 Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
1-0 OUT_MODE Dead-band Output Mode Control
Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 2-28 .
This allows you to selectively enable or bypass the dead-band generation for the falling-edge
and rising-edge delay.
00 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA
and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper
submodule.
In this mode, the POLSEL and IN_MODE bits have no effect.
01 Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight
through to the EPWMxA input of the PWM-chopper submodule.
The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is
determined by DBCTL[IN_MODE].
10 The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is
determined by DBCTL[IN_MODE].
Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight
through to the EPWMxB input of the PWM-chopper submodule.
11 Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge
delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].
Registers 104 SPRU791D – November 2004 – Revised October 2007
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