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4.5 PWM-Chopper Submodule Control Register
PWM-Chopper Submodule Control Register
Figure 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED)
15 10 9 8
Reserved DEL
R-0 R/W-0
7 0
DEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
Bits Name Value Description
15-10 Reserved Reserved
9-0 DEL Rising Edge Delay Count. 10-bit counter.
Figure 4-15. Dead-Band Generator Falling Edge Delay Register (DBFED)
15 10 9 8
Reserved DEL
R-0 R/W-0
7 0
DEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-15. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
Bits Name Description
15-10 Reserved Reserved
9-0 DEL Falling Edge Delay Count. 10-bit counter
Figure 4-16 and Table 4-16 provide the definitions for the PWM-chopper submodule control register.
Figure 4-16. PWM-Chopper Control Register (PCCTL)
15 11 10 8
Reserved CHPDUTY
R-0 R/W-0
7 5 4 1 0
CHPFREQ OSHTWTH CHPEN
R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-16. PWM-Chopper Control Register (PCCTL) Bit Descriptions
Bits Name Value Description
15-11 Reserved Reserved
SPRU791D – November 2004 – Revised October 2007 Registers 105
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