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Event-Trigger Submodule Registers
Table 4-25. Event-Trigger Flag Register (ETFLG) Field Descriptions
Bits Name Value Description
15-4 Reserved Reserved
3 SOCB Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
0 Indicates no EPWMxSOCB event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The
EPWMxSOCB output will continue to be generated even if the flag bit is set.
2 SOCA Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit
is set.
0 Indicates no event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The
EPWMxSOCA output will continue to be generated even if the flag bit is set.
1 Reserved Reserved
0 INT Latched ePWM Interrupt (EPWMx_INT) Status Flag
0 Indicates no event occurred
1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be
generated until the flag bit is cleared. Up to one interrupt can be pending while the
ETFLG[INT] bit is still set. If an interrupt is pending, it will not be generated until after the
ETFLG[INT] bit is cleared. Refer to Figure 2-41 .
Figure 4-26. Event-Trigger Clear Register (ETCLR)
15 8
Reserved
R = 0
7 4 3 2 1 0
Reserved SOCB SOCA Reserved INT
R-0 R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-26. Event-Trigger Clear Register (ETCLR) Field Descriptions
Bits Name Value Description
15-4 Reserved Reserved
3 SOCB ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCB] flag bit
2 SOCA ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCA] flag bit
1 Reserved Reserved
0 INT ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated
114 Registers SPRU791D – November 2004 – Revised October 2007
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