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Latch
Generate
interrupt
pulse
when
input = 1
2-bit
Counter
Set
Clear
1
0
0
Clear CNT
Inc CNT
ETPS[INTCNT]
ETPS[INTPRD]
ETCLR[INT]
EPWMxINT
ETFRC[INT]
ETSEL[INT]
ETFLG[INT]
ETSEL[INTSEL]
000
001
010
011
100
101
111
101
0
0
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
CTR=Zero
CTR=PRD
Event-Trigger (ET) Submodule
The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT])
register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they
reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops
counting and its output is set. The counter is only cleared when an interrupt is sent to the PIE.
When ETPS[INTCNT] reaches ETPS[INTPRD] the one of the following behaviors will occur:
• If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
• If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
• If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be
reset (so no interrupts are generated). Writing a 1 to the ETFRC[INT] bit will increment the event counter
INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the
counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored.
The above definition means that you can generate an interrupt on every event, on every second event, or
on every third event. An interrupt cannot be generated on every fourth or more events.
Figure 2-41. Event-Trigger Interrupt Generator
Figure 2-42 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The
ETPS[SOCACNT] counter and ETPS[SOCAPRD] period values behave similarly to the interrupt generator
except that the pulses are continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a
pulse is generated, but it does not stop further pulse generation. The enable/disable bit ETSEL[SOCAEN]
stops pulse generation, but input events can still be counted until the period value is reached as with the
interrupt generation logic. The event that will trigger an SOCA and SOCB pulse can be configured
separately in the ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same
events that can be specified for the interrupt generation logic.
66 ePWM Submodules SPRU791D – November 2004 – Revised October 2007
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