Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsPMIC - AC/DC converter, offline switcher UC3844N Boost, Buck, Flyback, Forward Frequency control SOIC 8

www.ti.com

FEATURES DESCRIPTION

BLOCK DIAGRAM

A/B

7 12

5 9

GROUND

4 7

2 3

1 1COMP

3 5

CURRENT

SENSE

34 V

2.50 V

OSC

UVLO

S/R

5 V

REF

VREF

Good

Logic

Internal

BIAS

Error

Amp

1 V

CURRENT

SENSE

COMPARATOR

PWM

LATCH

8 14

REF

5 V

50 mA

106

OUTPUT

POWER

GROUND

Note 1:

Note 2:

A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.

Toggle flip flop used only in 1844 and 1845.

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

CURRENT MODE PWM CONTROLLER

• Optimized For Off-line and DC-to-DC

The UC1842/3/4/5 family of control devices provides

Converters

the necessary features to implement off-line or

dc-to-dc fixed frequency current mode control

• Low Start-Up Current (<1 mA)

schemes with a minimal external parts count.

• Automatic Feed Forward Compensation

Internally implemented circuits include under-voltage

• Pulse-by-Pulse Current Limiting

lockout featuring start up current less than 1 mA, a

precision reference trimmed for accuracy at the error

• Enhanced Load Response Characteristics

amp input, logic to insure latched operation, a PWM

• Under-Voltage Lockout With Hysteresis

comparator which also provides current limit control,

• Double Pulse Suppression

and a totem pole output stage designed to source or

sink high peak current. The output stage, suitable for

• High Current Totem Pole Output

driving N-Channel MOSFETs, is low in the off state.

• Internally Trimmed Bandgap Reference

Differences between members of this family are the

• 500-kHz Operation

under-voltage lockout thresholds and maximum duty

• Low R

Error Amp

cycle ranges. The UC1842 and UC1844 have UVLO

thresholds of 16 V

and 10 V

OFF

, ideally suited to

off-line applications. The corresponding thresholds

for the UC1843 and UC1845 are 8.4 V and 7.6 V.

The UC1842 and UC1843 can operate to duty cycles

approaching 100%. A range of zero to 50% is

obtained by the UC1844 and UC1845 by the addition

of an internal toggle flip flop which blanks the output

off every other clock cycle.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS (1) UNIT Low impedance source Supply voltage 30 V ICC < 30 mA Self Limiting ±1 A Output current 5 µJ Output energy (capacitive load) Analog inputs (Pins 2, 3) –0.3 V to 6.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) θJC θJA J 28 (1) 125-160 N 25 110 (2) SOIC-8 D8 42 84-160 (2) SOIC-14 D14 35 50-120 (2) CFP-14 W 5.49°C/W 175.4C/W PLCC-20 Q 34 43-75 (2) PACKAGE DIL-8 (1) (2) θJC data values stated were derived from MIL-STD-1835B.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V; RT = 10 kΩ; CT = 3.3 nF, TA = TJ. PARAMETER TEST CONDITIONS UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 UNIT MIN TYP MAX MIN TYP MAX 2.45 2.50 2.55 2.42 2.50 2.58 V –0.3 –1 –0.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 ERROR AMP CONFIGURATION Error amp can source or sink up to 0.5 mA. 2.5 V 0.5 mA + VFB ZI _ 2 COMP ZF 1 UNDER-VOLTAGE LOCKOUT During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 OSCILLATOR SECTION 8 30 4 CT GROUND 100 10 t d − ms RT/CT Timing Resistance vs Frequency Deadtime vs CT (RT >5 kW) RT RT − (k W) VREF 3 5 1 0.3 1 2.2 4.7 1.72 For RT> 5 K f ~ RTCT 10 22 CT − nF 47 30 10 3 100 100 1k OUTPUT SATURATION CHARACTERISTICS 4 VCC = 15 V Saturation Voltage − V 3 TA = 25°C TA = −55°C 2 SOURCE SAT (VCC − VOH) 1 SINK SAT (VOL) 0 .01 .02 .03 .04 .05 .07 .1 .
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 OPEN-LOOP LABORATORY FIXTURE High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. VREF R1 2N2222 4.7 kW 100 kW 1 kW ERROR AMP ADJUST 5 kW 4.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 www.ti.com SLUS223C – APRIL 1997 – REVISED JUNE 2007 OFFLINE FLYBACK REGULATOR T1 R1 5Ω1W 117 VAC D6 U9D946 L1 +6 V VARO VM 68 C9 3300 pF 600 V R12 4.7 kΩ 2W C1 250 µF 250 V R2 56 kΩ 2W N5 NP C10 4700 µF 10 V C11 4700 µF 10 V COM D4 1N3613 D7 UF81002 +12 V R4 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UC2842D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2842DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC2843D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2843DTR SOIC D 14 2500 330.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2842D8TR SOIC UC2842DTR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 28.6 UC2843D8TR SOIC UC2843DTR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 UC2844D8TR 28.6 SOIC D 8 2500 340.5 338.1 20.6 UC2844DTR SOIC D 14 2500 333.2 345.9 28.6 UC2845D8TR SOIC D 8 2500 340.
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MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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