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Voltage Monitoring (RPW/ERWM)
26
Functions
Multiple Protection Models (ERWM-VM1 / VM2)
Operating mode
PF (phase loss) – It occurs when the voltage of one of the phases drops below 70% of the
supply voltage. The maximum time delay is 350 ms for both the fault detection and the
return of the ERWM to normal operation.
Timing diagram
Output
15-18
15-16
L1
L2
L3
LED U
LED R
LED F
Ts
< 70%L2 < 70%L3< 70%L1
Supply voltage
L1-L2-L3
>Un (overvoltage) – It occurs after the rated tripping voltage (Un) (208 to 480 V) and the
tripping overvoltage percentage (>Un) (3 to 15%) are selected. The time delay is defined
by the time scale (1 to 30 s) or disabled (OFF) acting in a maximum of 350 ms. The
selected time delay is for both the fault detection and the return of the ERWM to normal
operation.
Timing diagram
Output
15-18
15-16
>Un
>Un - 2%
Un
LED U
LED R
LED F
Ts T T<T <T
Supply voltage
L1-L2-L3
Asy (unbalance) – It occurs when the voltage of one, two or three of the phases vary,
calculating the average value of the three phases and also the greatest voltage variation
value by the average value. The worst voltage variation case is taken into account in the
unbalance calculation. The time delay is defined by the time scale (1 to 30 s) or disabled
(OFF) acting in a maximum of 350 ms. The selected time delay is for both the fault
detection and the return of the ERWM to normal operation.
Timing diagram
Output
15-18
15-16
Asy
L3
L2
L1
Asy-hyst
Asy
Asy-hyst
LED U
LED R
LED F
Ts T
Supply voltage
L1-L2-L3
T T T
<T
Operating mode
PS (phase sequence
1)
– It occurs when the phases are not connected in the correct
sequence (L1-L2-L3) or even when a phase inversion occurs during operation. The
maximum time delay is 350 ms for both the fault detection and the return of the EWM to
normal operation. Only the ERWM-VM1 measures phase sequence.
Timing diagram
Output
15-18
15-16
L1
L2
L3
LED U
LED R
LED F
Ts
Supply voltage
L1-L2-L3
L3-L2-L1 L1-L2-L3 L1-L2-L3L1-L3-L2
L1-L3-L2
L2-L1-L3
>Un (undervoltage) – It occurs after the rated tripping voltage (Un) (208 to 480 V) and the
tripping undervoltage percentage (>Un) (-3 to -15%) are selected. The time delay is
defined by the time scale (1 to 30 s) or disabled (OFF) acting in a maximum of 350 ms.
The selected time delay is for both the fault detection and the return of the ERWM to
normal operation.
Timing diagram
Output
15-18
15-16
Un
< Un - 2%
< Un
LED U
LED R
LED F
Ts T T<T
Supply voltage
L1-L2-L3
ND (neutral detection) – It occurs when the Neutral is not connected or it is disconnected
during operation, or also when the voltage rises above 20 V (due to unbalance in the
power grid). The maximum time delay is 350 ms for both the fault detection and the return
of the ERWM to normal operation. For neutral detection, it is necessary to provide a bridge
between terminals A and B; otherwise, the neutral will not be monitored.
Timing diagram
Output
15-18
15-16
L1
L2
L3
N
LED U
LED R
LED F
Ts
L1-L2-L3
Supply voltage
L1-L2-L3
L1-L2-L3N L1-L2-L3N L1-L2-L3N
L1-L2-L3
>20Vn