User's Manual

68 | Product Architecture
Aprisa SR+ Product Description
Product Architecture
The following are the key components of the Aprisa SR+ design:
Dual high performance ΣΔ fractional-N synthesizers to allow for full duplex operation
Wideband design electronically tunes over entire band
Proven low noise and spurious technology with over 50dB of SNR easily achieved
Power amplifier linearity
Unique temperature compensated pre-distortion system improves the efficiency and linearity of
the entire transmitter chain for non-constant envelope modulation systems
Simple IQ modulation line up reduces part count and improves MTBF
No mixing stages so no spurious responses present at the transmitter output
Digital control loops used for controlling power amplifier current and transmit output power, allows for
faster ramping and settling times with less error
Tx turn-on time limited primarily by PA ramping
Robust, closed-loop power control – fast, accurate power ramp up and down
Highly rugged N-Channel RF Power LDMOS transistors for the power amplifier
High efficiency (>50% PAE at 10W)
Very low thermal resistance (1.0°C/W)
Direct IQ down-conversion
Excellent Intermodulation distortion characteristics as channel filter can be placed directly after
the mixer without impacting noise figure
Digital channel filtering allows for multiple bandwidths with the same hardware
Low parts count and no crystal filters help to keep receiver performance extremely stable over
temperature
Integrated heat sink
Limits number of mechanical interfaces
Fin design optimized for natural convection
Monitoring and software control
Temperature control loop shuts down the transmitter when the temperature exceeds continuous
operation at 70°C
Monitoring of RSSI and PA current to ensure the RF hardware is functioning to specification