User manual

Hardware Platform
XAPP794 (v1.3) December 20, 2013 www.xilinx.com 32
This design is implemented in a Zynq-7000 AP SoC device (XC7Z020CLG484-1) using Vivado
2013.2 design tools. The PL hardware utilization for the implemented design is shown in
Tabl e 1 0 .
There are many advantages to implementing this system in a Zynq-7000 AP SoC:
• Processing-intensive pixel operations are efficiently implemented in the PL.
• Complex decision-making algorithms like automatic white balance and automatic
exposure are efficiently implemented in the PS.
• Processor operations can easily be modified or added to the PS.
• The hardware system can easily be expanded or customized by adding/removing
instances of Xilinx IP cores from the Xilinx IP catalog or third-party sources.
• The hardware system can be further customized by adding custom logic that either
interfaces to the PS or is totally independent.
• A choice of Zynq-7000 AP SoC sizes allows room to shrink or expand the hardware PL to
meet system requirements.
System Features
Processing System
• Two ARM Cortex™-A9 processors, each with a 32 KB instruction cache and a 32 KB data
cache, and a NEON coprocessor
• ARM processors at 800 MHz
• 512 KB of level-2 cache
• 256 KB of on-chip RAM
• 128 KB of on-chip ROM
• AMBA® AXI interconnect
• Multi-protocol, 32-bit DDR DRAM controller
• DDR3 DRAM at 533 MHz
• Standard peripheral interfaces including flash, USB, Ethernet, UART, I2C, and more
• High bandwidth interconnect to and from the PL
• Power domain independent of the PL
Table 10: Hardware Utilization
FPGA Components Total Available Used % Used
I/Os 200 58 29
LUTs 53,200 30,614 57
Registers 106,400 38,316 36
DSP48s 220 92 42
Block RAM
RAMB36E1/FIFO36E1s 140 36 26
RAMB18E1/FIFO18E1s 280 16 6
Notes:
1. Device resource utilization results are dependent on the implementation tool versions. Exact results can
vary. These numbers should be used as a guideline.