User manual

Hardware Platform
XAPP794 (v1.3) December 20, 2013 www.xilinx.com 35
In this design, the stream interface data width is set to 32 bits and the memory-mapped
interface width is 64 bits. The AXI VDMA is used in simple register direct mode, which removes
the area cost of the scatter gather feature. Initialization, status, and management registers in
the AXI VDMA core are accessed through an AXI4-Lite slave interface. To get the best possible
throughput for AXI VDMA instances, the maximum burst length is set to 16. The store and
forward feature of the AXI VDMA are enabled on both channels to improve system performance
and reduce the risk of system throttling.
For additional information about the AXI VDMA LogiCORE solution and the detailed product
guide, refer to the AXI VDMA product page:
w
ww.xilinx.com/products/intellectual-property/axi_video_dma
Video Processing Pipeline Details
Test Pattern Generator
The Xilinx Test Pattern Generator IP Core generates test patterns for Video System bring-up,
evaluation, and debug. The core provides a wide variety of tests patterns for debugging and
assessing video system color, quality, edge and motion performance, and quality issues. The
core can be inserted in an AXI4-Stream video interface that allows user-selectable
pass-through of system video signals or insertion of test patterns.
There are two AXI TPG cores in the image processing pipeline, as shown in Figure 34.
The first AXI TPG core can be used to insert defect pixels in the video processing pipeline to
test the performance of the AXI DPC core. The second AXI TPG core can be used to insert a
RGB test pattern into the video processing pipeline. In the final design, the two AXI TPG cores
are disabled and pass the video data without modification to the next core in the pipeline. For
additional information about the Test Pattern Generator LogiCORE solution and the detailed
product guide, see the Test Pattern Generator product page:
www.xilinx.com/products/intellectual-property/tpg
Defective Pixel Correction
The AXI Defective Pixel Correction (DPC) core is the first processing element in the image
processing pipeline, as shown in Figure 35.
X-Ref Target - Figure 34
Figure 34: AXI TPG Core Pipeline Position
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X-Ref Target - Figure 35
Figure 35: AXI DPC Core Pipeline Position
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Gamma
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