Datasheet

DS2482-100: Single-Channel 1-Wire Master
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Figure 5. 1-Wire Reset/Presence Detect Cycle
Pull-up DS2482 pull-down 1-W Slave pull down
t
RSTL
t
RSTH
RESET PULSE PRESENCE/SHORT DETECT
V
CC
V
IH1
V
IL1
0V
t
F1
t
SI
t
MSP
For presence pulse masking and pull-up details see Figure 3.
1-Wire Single Bit
Command Code
87h
Command Parameter
Bit Byte
Description
Generates a single 1-Wire time slot with a bit value ‘V’ as specified by the
bit byte at the 1-Wire line. A ‘V’ value of 0b generates a write-zero time
slot (Figure 6), a value of 1b generates a write-one slot, which also
functions as a read-data time slot (Figure 7). In either case the logic level
at the 1-Wire line is tested at t
MSR
and SBR is updated.
Typical Use
To perform single bit writes or reads at the 1-Wire line when single bit
communication is necessary (the exception).
Restriction
1-Wire activity must have ended before the DS2482-100 can process this
command.
Error Response
Command code and bit byte are not acknowledged if 1WB = 1 at the time
the command code is received and the command is ignored.
Command Duration
t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the first
bit (MS bit) of the bit byte.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
bit byte.
Read Pointer Position
Status register (for busy polling and data reading)
Status Bits Affected
1WB (set to 1 for t
SLOT
)
SBR is updated at t
MSR
DIR (may change its state)
Configuration Bits Affected
1WS, APU, SPU apply
Bit Allocation in the Bit Byte
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
V x x x x x x x
x = don’t care