Datasheet

DS2482-100: Single-Channel 1-Wire Master
15 of 22
I
2
C Definitions
The following terminology is commonly used to describe I
2
C data transfers. The timing references are defined in
Figure 10.
Figure 10. I²C Timing Diagram
SCL
SDA
STOP START
t
BUF
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
HIGH
t
SU:DAT
Repeated
START
t
SU:STA
t
F
t
HD:STA
t
SP
t
SU:STO
Spike
Suppression
NOTE: TIMING IS REFERENCED TO V
ILMAX
AND V
IHMIN
.
Bus Idle or Not Busy: Both SDA and SCL are inactive and in their logic HIGH states.
START Condition: To initiate communication with a slave, the master must generate a START condition. A
START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition: To end communication with a slave, the master must generate a STOP condition. A STOP
condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition: Repeated starts are commonly used for read accesses to select a specific data
source or address to read from. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without leaving the bus idle after a STOP condition.
Data Valid: With the exception of the START and STOP condition, transitions of SDA may occur only during the
LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus
the required setup and hold time (t
HD:DAT
after the falling edge of SCL and t
SU:DAT
before the rising edge of SCL, see
Figure 10). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge
of SCL.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
t
SU:DAT
+ t
R
in Figure 10) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge: Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the
receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device
that acknowledges must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW
during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (t
HD:DAT
after
the falling edge of SCL and t
SU:DAT
before the rising edge of SCL).
Not Acknowledged by Slave: A slave device may be unable to receive or transmit data, e.g., because it is busy
performing some real-time function. In this case the slave device does not acknowledge its slave address and
leaves the SDA line HIGH.