Datasheet

DS2482-100: Single-Channel 1-Wire Master
4 of 22
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time t
HD:DAT
(Notes 12, 13) 0.9 µs
Data Setup Time t
SU:DAT
(Note 14) 250 ns
Setup Time for STOP
Condition
t
SU:STO
0.6 µs
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3 µs
Capacitive Load for Each Bus
Line
C
B
(Note 15) 400 pF
Oscillator Warm-Up Time t
OSCWUP
(Note 16) 100 µs
Note 1: Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive.
Note 2: With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on
threshold V
IL1
may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not
exceed 300pF.
Note 3: Active pullup guaranteed to turn on between V
IL1MAX
and V
IH1MIN
.
Note 4: Active or resistive pullup choice is configurable.
Note 5: Except for t
F1
, all 1-Wire timing specifications and t
APUOT
are derived from the same timing circuit. Therefore, if one of these
parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in
the same direction and by the same degree.
Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew
rate is slightly faster.
Note 7: Fall time high-to-low (t
F1
) is derived from PD
SRC
, referenced from 0.9 × V
CC
to 0.1 × V
CC
.
Note 8: Presence-pulse masking only applies to standard speed.
Note 9: All I²C timing values are referred to V
IHmin
and V
ILmax
levels.
Note 10: Applies to SDA, SCL, and AD0, AD1.
Note 11: The I/O pins of the DS2482-100 do not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 12: The DS2482-100 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Note 13: The maximum t
HD
:
DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 14:
A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t
SU
:
DAT
≥250ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t
SU
:
DAT
= 1000 + 250 = 1250ns
(according to the standard-mode I²C-bus specification) before the SCL line is released.
Note 15: C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to I²C-bus Specification
v2.1 are allowed.
Note 16: I²C communication should not take place for the max t
OSCWUP
time following a power-on reset.
PIN DESCRIPTION
PIN NAME FUNCTION
1 V
CC
Power Supply Input
2 IO IO Driver for 1-Wire Line
3 GND Ground Reference
4 SCL I²C Serial Clock Input. Must be tied to V
CC
through a pullup resistor.
5 SDA I²C Serial Data Input/Output. Must be tied to V
CC
through a pullup resistor.
6 PCTLZ
Active-low control output for an external P-channel MOSFET to provide extra power to
the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily
to operate.
7 AD1
8
AD0
I²C Address Inputs. Must be tied to V
CC
or GND. These inputs determine the I²C slave
address of the device (see Figure 9).