Technical Handbook

Table Of Contents
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Block Diagram:
Figure 9-12 RMA1215A Block Diagram.
Block description.
CPU
The CPU is an 80C188EB micro controller with address decoding unit and two UARTs. Only
one of these UARTs is utilised for serial communication. The other has been mapped as a par-
allel IO port. The operating frequency of the CPU is 20 MHz provided by an external 40 MHz
oscillator.
WATCHDOG AND BATTERY
A watchdog resets the CPU at power up and if the CPU does not toggle the watchdog reset bit
within app. 1.6 sec. intervals, or if the +5V supply voltage goes below the battery voltage. In
the latter case battery voltage will beconnected to the RAM and RTC. Removal of the battery
or jumper P2 will cause the RESET line to go low and inhibit any function on the module. If a
battery is not available, function can be achieved by shorting the battery socket.The battery
can be disconnected by removing jumper P2 when the module is being stored.The battery
voltage is measured using an opto coupler switch in order not to discharge the battery. The
battery providesapproximately one month memory retention at continuous use (system power
turned off).
INTERRUPT CIRCUITRY
The interrupt circuitry combines several interrupts into the 5 interrupt inputs of the CPU.
DISPLAY
The display used is a 20 characters by 4 lines LCD.
KEYPAD
+
-
Ident
speaker
channels.
IIC bus
Interrupts
Analog
voltages
Det.
ident
Jumper
CPU
CTRL
port
CTRL
port
CTRL
port
RMS bus
Double
UART
CTRL
port
Analog
MUX
Analog
MUX
Analog
MUX
Interrupt
circutry
CTRL
port
A
D
Keypad
Display
KD1214A
RM1213A
Watchdog
IIC
controller
Battery
RESET
Memory
RAM
EPROM
EEPROM
Real time
clock
RS232
drivers
Three serial
HBK588-1