Technical Handbook

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9.1.2 MO1212A Monitor
General Description:
The MO1212A module digital converts and processes NAV parameters, compares them with
programmable limits and reports alarm situations to the Station Control on TCA1218A (chap-
ter 9.1.3) and the RMS.
Block Diagram:
See Figure 9-2.
Block Description:
LF_FRONT:
The analog signals from MF1219A Monitor Frontend are multiplexed and digitized, and the
difference frequency (DF) pulse train is counted as a 12 bits value. These digital values are
multiplexed into the FIFO along with the DC loop (DL_Detect[3:0]), External (Ext_Val[11:0])
and test channels. The FIFO is seven words deep, and the sampling frequency is 640 Hz/
channel. Much of the functionality of LF-Front is handled by a FPGA NMP101A which is
described in chapter 9.1.2.1.
DSP_FILTER
performs all filtering in the Monitor. Data is read from the LF_FRONTEND FIFO, AC data are
FFT analyzed and for the DC data mean values are calculated. The calculated parameters
are written to the COMPARATOR. DSP_FILTER consists of a TMS320C31 DSP, a memory
block and a reset/watchdog circuit.
COMPARATOR
compares the parameters received from DSP_FILTER with the programmed upper and lower
alarm limits. Alarm data are passed on to the Station Control and Terminator (on TCA1218A,
chapter 9.1.3) on a dedicated bus. The COMPARATOR generates both instantanous and
delayed alarms. The delayed signal is sent only if the alarm is still present after the pro-
grammed delay period. All parameters, alarm and warning data are passed on to the RMS via
an output FIFO (warning information is treated by the RMS). The alarm and warning limits and
delays are stored in the local EEPROM. Much of the functionallity of COMPARATOR is han-
dled by two FPGAs NMP102A and NMP103A described in chapter 9.1.2.2.
9.1.2.1 NMP101A Monitor Digital Frontend
General description:
NMP101A is a FPGA in the LF-FRONT block. It serves as an interface between the (digi-
tized) inputs from the monitor frontend MF1219A and the DSP_FILTER block. NMP101A is
based on the Actel ACT1020 FPGA. For electrical specifications see the ACT1020 datasheet.
Block diagram:
See Figure 9-2.
Block description:
REF COUNTER
divides the system clock (4.9152 MHz) for use in channel addressing. It also generates the
read/convert puls to the external ADC.