User Guide

3-16 Chapter 3
! CAS Latency (Tcl):
You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM
specification.
Bottom of 32-bit[31:24] IO:
This item selects the mode for the Bottom of 32-bit[31:24] IO function.
S/W memory hole Remapping:
This item enables or disables the S/W memory hole Remapping function.
H/W memory hole Remapping:
This item enables or disables the H/W memory hole Remapping function.
MTRR mapping mode
The item selects the MTRR mapping mode. The MTRR (Memory-Type and Range Registers) controls
the access and cacheability of memory regions in the processor.
# Back to Advanced Chipset Features Setup Menu:
# LDT & PCI Bus Control:
Click <Enter> key to enter its submenu:
Phoenix – Award WorkstationBIOS CMOS Setup Utility
LDT & PCI Bus Control
LDT Configuration Enabled Item Help
Upstream LDT Bus Width 16 bit
Downstream LDT Bus Width 16 bit
LDT Bus Frequency Auto
PCIE Reset Delay Disabled
↑↓:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
LDT Configuration:
This item enables or disables the LDT Configuration function.
Upstream LDT Bus Width:
This item sets the value for the Upstream LDT Bus Width.
AT8