User guide

128 RealCT Direct API Developer Guide
Chapter 4: E1 Networking
Using Internal Signaling Streams
The E1 board has internal streams that hold data received on
the line. Streams 17 and 19 hold signaling bits from trunks A
and B, respectively. Streams 16 and 18 hold data from trunks A
and B, respectively.
Within streams 17 and 19, 8-bit timeslots hold the signaling
data. The internal MVIP timeslots hold signaling bits the same
way they are transmitted in the E1 timeslot 16: the first nibble
holds signaling bits for line n and the second nibble holds
signaling bits for line n+15.
For example, timeslot 0 in stream 17 holds signaling bits for line
0 and line 15. Timeslot 1 holds signaling bits for line 1 and line
16, and so on through timeslot 14, which holds signaling bits for
lines 14 and 29. If timeslot 0 transmits the value 0x9D, then line
0 is transmitting ABCD=0x9=1001, and line 15 is transmitting
ABCD=0xD=1101.
Access the signaling bits using the SET_OUTPUT and
SAMPLE_INPUT MVIP functions. Applications can use these
functions to set and retrieve signaling bits directly from the
hardware instead of relying on higher level device functions
such as RHT_GET_LINE and RHT_GET_STATUS. Access to
low level signaling bits should only be used for tracing purposes,
since it can interfere with normal device functions such as
RHT_ON_HOOK.
To write bits to a specific internal stream/timeslot, put the
timeslot in message mode and use SET_OUTPUT. The
hardware takes the bits you write to the signaling streams and
sends them as signaling bits. To read bits from a specific
stream/timeslot, use SAMPLE_INPUT. See the RealCT Direct
API Reference Manual for more information about
SET_OUTPUT and SAMPLE_INPUT.
The E1 board receives data for lines 0 through 29 in internal
streams 16 and 18, timeslots 0 through 29. For information
about switching data received in streams 16 and 18 over the
CT bus, see Chapter 5, MVIP-90, on page 143, and Chapter 6,
MVIP-95, on page 183.