User guide

216 RealCT Direct API Developer Guide
Chapter 6: MVIP-95
Configuring the H.100 Clock for the MVIP-90 Bus
Defining H.100 Compatibility Clocks
Boards connected in an MVIP bus use an 8-kHz clock signal to
synchronize frames. One H.100 compliant board in the bus
drives the clock. All other boards receive their clock signal
through the 8-kHz clock signal set by the H.100 compliant
board.
The H.100 provides clocks that are compatible with the
MVIP-90 clocks. These are shown in Table 34:
Table 34. H.100 Compatibility Clocks
If you have an T1 or E1 board in the system, that board should
drive the /F0 clock. These boards get timing information for T1
and E1 signals from the network. All other boards in the system
should receive the clock signal from the MVIP bus. If there are
no T1 or E1 boards in the system, an H.100 compliant board can
use the internal oscillator to drive the clock. Vantage VRS,
Vantage VPS, and RDSP/xx000 boards can not set the MVIP
clock. They must receive the clock from the MVIP bus.
You can also specify that boards use SEC8K as a backup signal.
SEC8K is used as a fallback if the primary signal fails. As with
the primary signal, only one board drives the SEC8K clock.
H.100 clock MVIP-90 Clock
/FR_COMP /F0
/C4 /C4
C2 C2
CT_NETREF SEC8K