User guide

August 2001 75

Using Internal Signaling Streams

The T1 board has internal streams that hold data received on

the line. The board holds data for lines 0 through 23 in internal

streams 16 and 18, timeslots 0 through 23. It holds signaling

bits (ABCD) for lines 0 through 23 in internal timeslots 17 and

19, timeslots 0 through 23.

Access the signaling bits using the SET_OUTPUT and

SAMPLE_INPUT MVIP functions. Applications can use these

functions to set and retrieve signaling bits directly from the

hardware instead of relying on higher level driver functions

such as RHT_GET_LINE and RHT_GET_STATUS. Access to

low level signaling bits should only be used for tracing purposes,

since it can interfere with normal driver functions such as

RHT_ON_HOOK.

To write bits to a specific internal stream/timeslot, put the

timeslot in message mode and use SET_OUTPUT. The

hardware takes the bits you write to the signaling streams and

sends them as signaling bits. To read bits from a specific

stream/timeslot, use SAMPLE_INPUT. See the RealCT Direct

API Reference Manual for more information about

SET_OUTPUT and SAMPLE_INPUT.

For information about switching data received in streams 16

and 18 over the CT bus, see Chapter 5, MVIP-90, on page 143,

and Chapter 6, MVIP-95, on page 183.