Datasheet

Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications

2.8 CMOS Asynchronous and Open Drain

Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,

and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain

signals are required to be asserted/deasserted for at least eight BCLKs in order for the

processor to recognize the proper signal state. See Section 2.13 for the DC

specifications. See Chapter 6 for additional timing requirements for entering and

leaving the low power states.

2.9 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain followed by any

other components within the system. A translation buffer should be used to connect to

the rest of the chain unless one of the other components is capable of accepting an

input of the appropriate voltage. Similar considerations must be made for TCK, TDO,

TMS, and TRST#. Two copies of each signal may be required with each driving a

different voltage level.

2.10 Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel

between Intel processors and chipset components to external thermal monitoring

devices. The Dual-Core Intel® Xeon® Processor 5200 Series contains Digital Thermal

Sensor (DTS) sprinkled both inside and outside the cores in a die. These sensors are

implemented as analog-to-digital converters calibrated at the factory for reasonable

accuracy to provide a digital representation of relative processor temperature. PECI

provides an interface to relay the highest DTS temperature within a die to external

devices for thermal/fan speed control. More detailed information may be found in the

Platform Environment Control Interface (PECI) Specification.

2.10.1 DC Characteristics

The PECI interface operates at a nominal voltage set by V

. The set of DC electrical

specifications shown in Table 2-10 is used with devices normally operating from a V

interface supply. V

nominal levels will vary between processor families. All PECI

devices will operate at the V

level determined by the processor installed in the

system. For specific nominal V

levels, refer to the appropriate processor EMTS.