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47

Land Listing

4 Land Listing

4.1 Dual-Core Intel® Xeon® Processor 5200 Series

Pin Assignments

This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a

listing of all processor lands ordered alphabetically by land name. Table 4-2 is

a listing of all processor lands ordered by land number.

4.1.1 Land Listing by Land Name

Table 4-1. Land Listing by Land Name

(Sheet 1 of 20)

Pin Name

Pin

No.

Signal Buffer

Type

Direction

A03# M5 Source Sync Input/Output

A04# P6 Source Sync Input/Output

A05# L5 Source Sync Input/Output

A06# L4 Source Sync Input/Output

A07# M4 Source Sync Input/Output

A08# R4 Source Sync Input/Output

A09# T5 Source Sync Input/Output

A10# U6 Source Sync Input/Output

A11# T4 Source Sync Input/Output

A12# U5 Source Sync Input/Output

A13# U4 Source Sync Input/Output

A14# V5 Source Sync Input/Output

A15# V4 Source Sync Input/Output

A16# W5 Source Sync Input/Output

A17# AB6 Source Sync Input/Output

A18# W6 Source Sync Input/Output

A19# Y6 Source Sync Input/Output

A20# Y4 Source Sync Input/Output

A20M# K3 CMOS ASync Input

A21# AA4 Source Sync Input/Output

A22# AD6 Source Sync Input/Output

A23# AA5 Source Sync Input/Output

A24# AB5 Source Sync Input/Output

A25# AC5 Source Sync Input/Output

A26# AB4 Source Sync Input/Output

A27# AF5 Source Sync Input/Output

A28# AF4 Source Sync Input/Output

A29# AG6 Source Sync Input/Output

A30# AG4 Source Sync Input/Output

A31# AG5 Source Sync Input/Output

A32# AH4 Source Sync Input/Output

A33# AH5 Source Sync Input/Output

A34# AJ5 Source Sync Input/Output

A35# AJ6 Source Sync Input/Output

A36# N4 Source Sync Input/Output

A37# P5 Source Sync Input/Output

ADS# D2 Common Clk Input/Output

ADSTB0# R6 Source Sync Input/Output

ADSTB1# AD5 Source Sync Input/Output

AP0# U2 Common Clk Input/Output

AP1# U3 Common Clk Input/Output

BCLK0 F28 Clk Input

BCLK1 G28 Clk Input

BINIT# AD3 Common Clk Input/Output

BNR# C2 Common Clk Input/Output

BPM0# AJ2 Common Clk Input/Output

BPM1# AJ1 Common Clk Output

BPM2# AD2 Common Clk Output

BPM3# AG2 Common Clk Input/Output

BPM4# AF2 Common Clk Output

BPM5# AG3 Common Clk Input/Output

BPRI# G8 Common Clk Input

BR0# F3 Common Clk Input/Output

BR1# H5 Common Clk Input

BSEL0 G29 CMOS ASync Output

BSEL1 H30 CMOS ASync Output

BSEL2 G30 CMOS Async Output

D00# B4 Source Sync Input/Output

Table 4-1. Land Listing by Land Name

(Sheet 2 of 20)

Pin Name

Pin

No.

Signal Buffer

Type

Direction