Datasheet

Features

7 Features

7.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The Dual-Core Intel®

Xeon® Processor 5200 Series samples its hardware configuration at reset, on the

active-to-inactive transition of RESET#. For specifics on these options, please refer to

Table 7-1.

The sampled information configures the processor for subsequent operation. These

configuration options cannot be changed except by another reset. All external resets

reconfigure the processor, for configuration purposes, the processor does not

distinguish between a “warm” reset (PWRGOOD signal remains asserted) and a

“power-on” reset.

Notes:

1. Asserting this signal during RESET# will select the corresponding option.

2. Address lands not identified in this table as configuration options should not be asserted during RESET#.

Disabling of any of the cores within the Dual-Core Intel® Xeon® Processor 5200 Series

must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This

MSR will allow for the disabling of a single core per die within the package.

7.2 Clock Control and Low Power States

The Dual-Core Intel® Xeon® Processor 5200 Series supports the Extended HALT state

(also referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce

power consumption by stopping the clock to internal sections of the processor,

depending on each particular state. See Figure 7-1 for a visual representation of the

processor low power states. The Extended HALT state is a lower power state than the

HALT state or Stop Grant state.

The Extended HALT state must be enabled via the BIOS for the processor to

remain within its specifications. For processors that are already running at the

lowest bus to core frequency ratio for its nominal operating point, the processor will

transition to the HALT state instead of the Extended HALT state.

The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In

a multiprocessor system, all the STPCLK# signals are bussed together, thus all

processors are affected in unison. When the STPCLK# signal is asserted, the processor

enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each

processor die. The chipset needs to account for a variable number of processors

asserting the Stop Grant SBC on the bus before allowing the processor to be

transitioned into one of the lower processor power states.

Table 7-1. Power-On Configuration Option Lands

Configuration Option Land Name Notes

Output tri state SMI# 1,2

Execute BIST (Built-In Self Test) A3# 1,2

Disable MCERR# observation A9# 1,2

Disable BINIT# observation A10# 1,2

Symmetric agent arbitration ID BR[1:0]# 1,2