Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet ■ ■ ■ ■ ■ ■ ■ Available at 2 GHz, 2.10 GHz, 2.20 GHz, 2.30 GHz, 2.40 GHz, 2.50 GHz, 2.60 GHz, 2.70 GHz, and 2.
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Contents 1 Introduction .................................................................................................................. 9 1.1 1.2 2 Electrical Specifications ........................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3 System Bus and GTLREF ...................................................................................13 Power and Ground Pins .............................................
5 Pin Listing and Signal Definitions..................................................................... 59 5.1 5.2 6 Thermal Specifications and Design Considerations ................................. 81 6.1 7 7.3 8.3 8.4 Introduction ......................................................................................................... 91 Mechanical Specifications................................................................................... 92 8.2.
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 VCCVID Pin Voltage and Current Requirements ................................................15 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17 Phase Lock Loop (PLL) Filter Requirements ......................................................17 VCC Static and Transient Tolerance.............................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 6 References.......................................................................................................... 11 VCCVID Pin Voltage Requirements.................................................................... 15 Voltage Identification Definition........................................................................... 16 System Bus Pin Groups ...........................
Revision History Revision Description Date -002 Updated document with 2.10 GHz and 2.20 GHz specifications. November 2002 -003 Added 2.30 GHz and 2.40 GHz specifications. March 2003 -004 Added 2.50 GHz and 2.60 GHz specifications. Updated thermal specifications and thermal monitor sections. Updated PROCHOT# pin definition. June 2003 -005 Updated Title page. August 2003 -006 Added 2.70 GHz specifications. Updated Table 20 and Figure 11. September 2003 -007 Added 2.80 GHz specifications.
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Introduction Introduction 1 The Intel® Celeron® processor on 0.13 micron process and in the 478-pin package uses Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron processor on 0.13 micron process maintains the tradition of compatibility with IA-32 software. In this document, the Celeron processor on 0.
Introduction “System Bus” refers to the interface between the processor and system core logic (the chipset components). The system bus is a multiprocessing interface to processors, memory, and I/O. 1.1.1 Processor Packaging Terminology The following are commonly used terms: • Intel® Celeron® processor on 0.13 micron process and in the 478-pin package (also referred as the Intel® Celeron® processor on 0.13 micron process or processor) — 0.
Introduction 1.2 References The following documents should be referenced for additional information: Table 1. References Document Intel® Intel® Pentium® Document Number/Source 4 Processor in the 478 Pin Package and 850 Chipset Platform Design Guide http://developer.intel.com/design/ pentium4/guides/249888.htm Intel® Pentium® 4 Processor in the 478 Pin Package and Intel® 845 Chipset Platform for DDR Design Guide http://developer.intel.com/design/ chipsets/designex/298605.
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Electrical Specifications Electrical Specifications 2.1 2 System Bus and GTLREF Most Celeron processor on 0.13 micron process system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Like the Intel£ Pentium£ 4 processor, the termination voltage level for the Celeron processor on 0.
Electrical Specifications 2.3.1 VCC Decoupling Regulator solutions must provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on or is entering or exiting low power states must be provided by the voltage regulator solution (VR).
Electrical Specifications 2.4 Voltage Identification The VID specification for Celeron processor on 0.13 micron process is supported by the Intel£ Pentium£ 4 Processor VR-Down Design Guidelines. The voltage set by the VID pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 7 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification.
Electrical Specifications Table 3. Voltage Identification Definition Processor Pins Vcc_max 2.4.1 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.450 0 1 1 1 1 1.
Electrical Specifications Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution L VCC VCCA CA PLL Processor Core VSSA CIO VCCIOPLL L . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz fpeak 1 MHz 66 MHz Passband fcore High Frequency Band Filter_Spec NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Electrical Specifications 2.5 Reserved, Unused Pins, and TESTHI[12:0] All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 5 for a processor pin listing, and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level.
Electrical Specifications 2.6 System Bus Signal Groups To simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Electrical Specifications 2.7 Asynchronous GTL+ Signals The Celeron processor on 0.13 micron process does not use CMOS voltage levels for any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals.
Electrical Specifications 2.10 Maximum Ratings Table 6 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Electrical Specifications Table 7. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes1 VCC for Processor at VID=1.475 V: 2 GHz 1.315 2.10 GHz 1.310 2.20 GHz 1.310 2.30 GHz 1.305 2.40 GHz 1.300 2.50 GHz 1.300 2.60 GHz 1.295 2.70 GHz 1.290 2.80 GHz 1.290 VCC for Processor at VID=1.500 V: VCC 2 GHz 1.340 2.10 GHz 1.335 2.20 GHz 1.335 2.30 GHz 1.330 2.40 GHz 1.325 2.50 GHz 1.325 2.60 GHz 1.320 2.70 GHz 1.315 2.80 GHz 1.
Electrical Specifications Table 7. Voltage and Current Specifications Symbol Parameter Min Typ Max Notes1 Unit ICC Stop-Grant 2 GHz 18 2.10 GHz 23 2.20 GHz 23 ISGNT 2.30 GHz 23 Islp 2.40 GHz 23 2.50 GHz 23 2.60 GHz 23 2.70 GHz 23 2.80 GHz A 9, 11, 12 8, 9 23 ITCC ICC TCC active ICC A ICC PLL ICC for PLL pins 60 mA 9 NOTES: Unless otherwise noted, all specifications in this table are based on the latest silicon measurements available at time of publication. 2.
Electrical Specifications Table 8. VCC Static and Transient Tolerance (Sheet 2 of 2) Voltage Deviation from VID Setting (V)1,2,3,4 ICC (A) Maximum Typical Minimum 55 –0.105 –0.145 –0.185 60 –0.114 –0.156 –0.197 65 –0.124 –0.166 –0.209 70 –0.133 –0.177 –0.222 NOTES: The loadline specifications include both static and transient limits. This table is intended to aid in reading discrete points on the following loadline figure and applies to any VID setting. 3.
Electrical Specifications Table 9. System Bus Differential BCLK Specifications Symbol Notes1 Parameter Min Typ Max Unit Fig VL Input Low Voltage –0.150 0.000 N/A V 8 VH Input High Voltage 0.660 0.710 0.850 V 8 VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 8, 9 2, 3, 4 VCROSS(rel) Relative Crossing Point V 8, 9 2, 3, 4, 5 ∆VCROSS Range of Crossing Points N/A N/A 0.140 V 8, 9 2, 6 VOV Overshoot N/A N/A VH + 0.3 V 8 7 VUS Undershoot –0.
Electrical Specifications Table 11. Asynchronous GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIH Input High Voltage Asynch GTL+ 1.10*GTLREF VCC V 2, 3, 4 VIL Input Low Voltage Asynch. GTL+ 0 0.
Electrical Specifications Table 13. ITPCLKOUT[1:0] DC Specifications Symbol Ron Parameter Buffer On Resistance Min Max Unit 27 46 Ω Notes1 2, 3 NOTES: Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. See Figure 5 for ITPCLKOUT[1:0] output buffer diagram. 1. Figure 5. ITPCLKOUT[1:0] Output Buffer Diagram VCC RON To Debug Port Processor Package RTEXT ITPCLKOUT Buff NOTES: 1.
Electrical Specifications 2.12 AGTL+ System Bus Specifications Routing topology recommendations can be found in the appropriate Platform Design Guide listed in Table 1. Termination resistors are not required for most AGTL+ signals because termination resistors are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation).
Electrical Specifications 2.13 System Bus AC Specifications The processor system bus timings specified in this section are defined at the processor silicon. See Chapter 5 for the Celeron processor on 0.13 micron process pin signal definitions. Table 16 through Table 21 list the AC specifications associated with the processor system bus. All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise specified.
Electrical Specifications Table 18. System Bus Source Synch AC Specifications AGTL+ Signal Group Max Unit Figure Notes1, 2, 3, 4 1.20 ns 12, 13 5 0.85 ns 13 5, 6 T22: TVAD: Source Synchronous Data Output Valid After Strobe 0.85 ns 13 5, 6 T23: TVBA: Source Synchronous Address Output Valid Before Strobe 1.88 ns 12 5, 6 T24: TVAA: Source Synchronous Address Output Valid After Strobe 1.88 ns 12 5, 7 T25: TSUSS: Source Synchronous Input Setup Time to Strobe 0.
Electrical Specifications Table 19. Miscellaneous Signals AC Specifications T# Parameter Min T35: Asynch GTL+ Input Pulse Width Max 2 Unit Figure Notes1, 2, 3, 4 BCLKs T36: PWRGOOD to RESET# deassertion time 1 ms 14 T37: PWRGOOD Inactive Pulse Width 10 10 BCLKs 14 5 T38: PROCHOT# pulse width 500 µs 15 6 0.5 s 17 5 BCLKs T39: THERMTRIP# to VCC Removal T40: FERR# Valid Delay from STPCLK# deassertion 0 Section 3 NOTES: 1.
Electrical Specifications Table 22. ITPCLKOUT[1:0] AC Specifications Parameter Min T65: ITPCLKOUT Delay T66: Slew Rate Typ Max Unit 400 560 ps 2 8 V/ns T67: ITPCLKOUT[1:0] High Time 3.89 5 6.17 ns T68: ITPCLKOUT[1:0] Low Time 3.89 5 6.17 ns Figure Notes 1, 2 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3.
Electrical Specifications Figure 7. TCK Clock Waveform 80% 50% 20% tr = T56, T58 (Rise Time) tf = T57, T59 (Fall Time) tp = T55 (TCK Period) Figure 8.
Electrical Specifications Figure 9. Differential Clock Crosspoint Specification 650 600 550 Crossing Point (mV) 550 mV 500 450 550 + 0.5(VHavg – 710) 400 250 + 0.5(VHavg – 710) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 Vhavg (mV) Figure 10.
Electrical Specifications Figure 11. System Bus Reset and Configuration Timings BCLK Tt Reset Ty Tv Tx Tw Configuration A[31:3], SMI#, INIT# Valid Configuration BR0# Valid Tv = T13 (RESET# pulse width) Tw = T45 (Reset configuration signals setup time) Tx = T46 (Reset configuration signals A[31:3], SMI#, and INIT# hold time) Ty = T47 (Reset configuration signal BR0# hold time) Figure 12. Source Synchronous 2X (Address) Timings T1 2.5 ns 5.0 ns T2 7.
Electrical Specifications Figure 13. Source Synchronous 4X Timings T0 T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync.
Electrical Specifications Figure 14. Power Up Sequence BCLK Vcc PWRGOOD Tc Td RESET# VCCVID Ta Tb VID_GOOD VID[4:0] Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time) Tc= T37 (PWRGOOD inactive pulse width) Td= T36 (PWRGOOD to RESET# de-assertion time) NOTE: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regulator control silicon.
Electrical Specifications Figure 16. Test Reset Timings V Tq T = T64 (TRST# Pulse Width), V=0.5*Vcc q T38 (PROCHOT# Pulse Width), V=GTLREF Figure 17. THERMTRIP# Power Down Sequence T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# driver is inactive when RESET# is active Figure 18. ITPCLKOUT Valid Delay Timing Tx BCLK ITPCLKOUT Tx = T65 = BCLK input to ITPCLKOUT output delay 38 Intel® Celeron® Processor on 0.
Electrical Specifications Figure 19. FERR#/PBE# Valid Delay Timing BCLK SG Ack system bus STPCLK# Ta FERR#/PBE# FERR# undefined PBE# undefined FERR# Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion) Note: FERR# / PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system bus. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE# signal is driven. FERR# is driven at all other times.
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System Bus Signal Quality Specifications System Bus Signal Quality Specifications 3 Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
System Bus Signal Quality Specifications Figure 21. BCLK Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 System Bus Signal Quality Specifications and Measurement Guidelines Various scenarios have been simulated to generate a set of AGTL+ layout guidelines that are available in the Platform Design Guideline.
System Bus Signal Quality Specifications Table 25. Ringback Specifications for PWRGOOD Input and TAP Signal Group Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure TAP and PWRGOOD 0→1 Vt+(max) TO Vt-(max) V 24 TAP and PWRGOOD 1→0 Vt-(min) TO Vt+(min) V 25 Notes1,2,3,4 NOTES: All signal integrity specifications are measured at the processor silicon. Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.
System Bus Signal Quality Specifications Figure 24. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max) Allowable Ringback Vss Figure 25. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0. Vss 44 Intel® Celeron® Processor on 0.
System Bus Signal Quality Specifications 3.3 System Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 26. The overshoot guideline limits transitions beyond VCC or VSS because of the fast signal edge rates.
System Bus Signal Quality Specifications 3.3.4 Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles.
System Bus Signal Quality Specifications 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However, most systems will have multiple overshoot and/or undershoot events, and each has its own set of parameters (duration, AF and magnitude).
System Bus Signal Quality Specifications Table 27. 1.525 V VID Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/ Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.800 –0.310 0.02 0.24 2.44 1.750 –0.260 0.03 0.26 2.63 1.700 –0.210 0.03 0.32 3.19 1.650 –0.160 0.11 1.05 10.00 1.600 –0.110 0.28 10.00 10.00 1.550 –0.060 1.25 10.00 10.
System Bus Signal Quality Specifications Figure 26. Maximum Acceptable Overshoot/Undershoot Waveform Time-dependent Overshoot VMAX VCC Maximum Absolute Overshoot GTLREF VOL VSS V MIN Maximum Absolute Undershoot Intel® Celeron® Processor on 0.
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Package Mechanical Specifications Package Mechanical Specifications 4 The Celeron processor on 0.13 micron process is packaged in a Flip-Chip Pin Grid Array (FC-PGA2) package. Components of the package include an integrated heat spreader (IHS), processor die, and the substrate that is the pin carrier. Mechanical specifications for the processor are given in this section. See Section 1.1. for a listing of terminology. The processor socket that accepts the Celeron processor on 0.
Package Mechanical Specifications Figure 28. Processor Package Table 30. Description Table for Processor Dimensions Dimension (mm) Code Letter A1 Notes Min Nominal Max 2.266 2.378 2.490 A2 0.980 1.080 1.180 B1 30.800 31.000 31.200 B2 30.800 31.000 31.200 C1 33.000 Includes Placement Tolerance C2 33.000 Includes Placement Tolerance D 34.900 35.000 35.100 D1 31.500 31.750 32.000 G1 13.970 Keep-In Zone Dimension G2 13.970 Keep-In Zone Dimension G3 1.
Package Mechanical Specifications Figure 29 shows the keep-in specification for pin-side components. The Celeron processor on 0.13 micron process may contain pin side capacitors mounted to the processor package. Figure 31 shows the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor substrate. Figure 29. Processor Cross-Section and Keep-In FCPGA 2 IHS Substrate 1.25mm 13.
Package Mechanical Specifications Figure 31. IHS Flatness Specification IHS SUBSTRATE NOTES: 1. Flatness is specified as overall, not per unit of length. 2. All Dimensions are in millimeters. 4.1 Package Load Specifications Table 31 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions.
Package Mechanical Specifications 4.2 Processor Insertion Specifications The Celeron processor on 0.13 micron process can be inserted and removed 15 times from a mPGA478B socket meeting the Intel£ Pentium£ 4 Processor 478-pin Socket (mPGA478B) Design Guidelines document. 4.3 Processor Mass Specifications Table 32 specifies the processor’s mass. This includes all components that make up the entire processor product. Table 32. Processor Mass Processor ® Mass (grams) ® Intel Celeron processor on 0.
Package Mechanical Specifications Figure 33.
Package Mechanical Specifications Figure 34.
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Pin Listing and Signal Definitions Pin Listing and Signal Definitions 5.1 5 Processor Pin Assignments Section 5.1 contains the pinlist for the Celeron processor on 0.13 micron process in Table 34 and Table 35. Table 34 is a listing of all processor pins ordered alphabetically by pin name. Table 35 is a listing of all processor pins ordered by pin number. Intel® Celeron® Processor on 0.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name 60 Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name 62 Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name 64 Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 34. Pin Listing by Pin Name Pin Name Pin # Signal Buffer Type Direction Table 34.
Pin Listing and Signal Definitions Table 35.
Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Number Pin # Pin Name Signal Buffer Type Direction Table 35.
Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Number Pin # 68 Pin Name Signal Buffer Type AF21 VCC Power/Other AF22 BCLK0 Bus Clock AF23 BCLK1 Bus Clock AF24 Table 35.
Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Number Pin # Pin Name Signal Buffer Type E6 TRST# TAP E7 VSS E8 VCC E9 Direction Input Table 35.
Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Number Pin # 70 Pin Name Signal Buffer Type Direction K6 VSS Power/Other K21 VSS Power/Other K22 DSTBN1# Source Synch Input/Output K23 D30# Source Synch Input/Output K24 VSS Power/Other K25 DP1# Common Clock Input/Output Input/Output Table 35.
Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Number Pin # Pin Name Signal Buffer Type Direction Table 35.
Pin Listing and Signal Definitions 5.2 Alphabetical Signals Reference Table 36. Signal Description (Sheet 1 of 8) Name Type Input/ Output A[35:3]# Description A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel® Celeron® processor on 0.13 micron process.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 4 of 8) Name DRDY# Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 5 of 8) Name Type IGNNE# Input Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 6 of 8) Name PROCHOT# Type Input/ Output Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 7 of 8) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Pin Listing and Signal Definitions Table 36. Signal Description (Sheet 8 of 8) Name Type Description TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 Ω pull-down resistor. VCCA Input VCCA provides isolated power for the internal processor core PLLs. Refer to Table 1 for the appropriate Platform Design Guide for details on implementation.
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Thermal Specifications and Design Considerations Thermal Specifications and Design Considerations 6 The Celeron processor on 0.13 micron process has an integrated heat spreader (IHS) for heatsink attachment that is intended to provide for multiple types of thermal solutions. This section provides information necessary for development of a thermal solution. See Figure 35 for an exploded view of an example Celeron processor on 0.13 micron process thermal solution. This is for illustration purposes.
Thermal Specifications and Design Considerations 6.1 Processor Thermal Specifications The Celeron processor 0.13 micron process requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 6.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system.
Thermal Specifications and Design Considerations Table 37. Processor Thermal Design Power Processor and Core Frequency Thermal Design Power 1,2 (W) Minimum TC (°C) Maximum TC (°C) 2 GHz 3 52.8 5 68 2.10 GHz 55.5 5 69 2.20 GHz 57.1 5 70 2.30 GHz 58.3 5 70 2.40 GHz 59.8 5 71 2.50 GHz 61.0 5 72 2.60 GHz 62.6 5 72 2.70 GHz 66.8 5 74 2.80 GHz 68.4 5 75 Notes For Processor with multiple VIDs: NOTES: 1. These values are specified at VCC_MAX for the processor.
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Features Features 7.1 7 Power-On Configuration Options Several configuration options can be configured by hardware. Celeron processor on 0.13 micron process sample their hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 38. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor.
Features 7.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state.
Features 7.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state.
Features 7.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should be asserted only when the processor is in the Stop Grant state.
Features specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guide for information on designing a thermal solution.
Features 7.3.1 Thermal Diode The Celeron processor on 0.13 micron process incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 39 and Table 40 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 39.
Boxed Processor Specifications Boxed Processor Specifications 8.1 8 Introduction The Celeron processor on 0.13 micron process will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators that build systems from motherboards and standard components. The boxed Celeron processor on 0.13 micron process will be supplied with a cooling solution.
Boxed Processor Specifications 8.2 Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Celeron processor on 0.13 micron process. The boxed processor will be shipped with an unattached fan heatsink. Figure 38 shows a mechanical representation of the boxed Celeron processor on 0.13 micron process. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 40. Top View Space Requirements for the Boxed Processor 8.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See the Intel£ Pentium£ 4 Processor in the 478-pin Package Thermal Design Guidelines for details on the processor weight and heatsink requirements. 8.2.
Boxed Processor Specifications heatsink attach clip assembly is latched to the retention tab features at each corner of the retention mechanism. The target load applied by the clips to the processor heat spreader for Intel’s reference design is 75 ±15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket.
Boxed Processor Specifications Figure 41. Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 2 +12 V 0.100" pin pitch, 0.025" square pin width. 3 SENSE Waldom/Molex P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3, or equivalent. 1 2 3 Table 41.
Boxed Processor Specifications Figure 42. MotherBoard Power Header Placement Relative to Processor Socket 96 Intel® Celeron® Processor on 0.
Boxed Processor Specifications 8.4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 8.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system and is ultimately the responsibility of the system integrator. The processor temperature is specified in Chapter 6.
Boxed Processor Specifications Figure 44. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 2 View) 8.4.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low.
Boxed Processor Specifications Figure 45. Boxed Processor Fan Heatsink Set Points Table 42. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed 33 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.
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Debug Tools Specifications Debug Tools Specifications 9 Refer to the ITP700 Debug Port Design Guide and the appropriate Platform Design Guide for more detailed information regarding debug tools specifications. 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron processor on 0.13 micron process systems.
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