Specifications

PC/II+p Board Technical Reference Manual 15
MT002615 ©1999-2001, Megatel Computer Corporation
3 Specification Summary
3.1 PC/II+p Board Specifications
Board Form Factor: 3.775 x 3.550 inch, PC/104 compliant
Board Type: FR4
Architecture: PC®/AT
Central Processing Unit: CPGA 321-Pin Socket, for Low-Power "Socket 7" or Compatible Processor
Accepts 321-Pin CPGA Processors or 296-Pin SPGA Low-Power
Processors (from Intel or AMD – see below for supported processors)
Full Socket 7 Compliance.
Intel Low-Power Pentium MMX Processor (166 Mhz and 266 MHz)
Local Bus Speed – 66 MHz
Superscalar (Pipelined) Architecture
32-Bit Cpu with 64-Bit Data Bus
Dual Pipeline
Integrated Pipelined Floating-Point Unit
Integrated Pipelined MMX Unit
Cache – Separate 16 KB Write-Back Data and 16 KB Code Caches
Voltages – Core 1.9V; I/O 2.5V
Package – PPGA-296
AMD K6-2E Embedded Processor (AMD-K6/-2E/233AMZ – 233 MHz)
Local Bus Speed – 66 MHz
Superscalar (6-Stage Pipelined) Architecture
10 Parallel Execution Units, 2-Level 8192-Entry Branch Prediction,
Out-of-Order Execution, Speculative Execution, Register Renaming
Integrated Pipelined Floating-Point Unit (IEEE 754/854)
Integrated Pipelined MMX Unit
Cache – Separate 32 KB Write-Back Data and 32 KB Code Caches
Decode Cache – 20 KB
Branch-Target Cache – 8K-Entry
Package – CPGA-321
Voltage – Core 1.9V; I/O – 3.3V
Cache Memory: L1 On-Chip Cache
32 KB or 64 KB – Separate Code/Data Organization
High performance write-back
Type of Cache and Additional Caching depends upon Processor
DMA: (7) Channels, 32-Bit addressing
Four 8-Bit Channels, Three 16-Bit Channels
Provides compatible DMA transfers
Provides Type F transfers
Timer/Counters: AT-compatible (8254 type) timers
for System Timer, Refresh Request and Speaker Output Use