Specifications

PC/II+p Board Technical Reference Manual 32

7 Functional Specifications

7.1 Bridge

See Bus, DRAM Memory, Peripheral Controllers, Section 7.2.

7.2 Bus, DRAM Memory, Peripheral Controllers

The PC/II+p board utilizes the ALI Aladdin M1531B north bridge controller for Socket 7 CPUs, and the ALI

Aladdin M1543C-B1 south bridge controller, to generate the PCI and ISA buses respectively.

The north bridge provides bridging between the 66 MHz Pentium-class host bus (FSB) and the 33 MHz PCI

bus. The north bridge's integrated memory controller also operates the on-board Synchronous DRAM using

a 64-bit data bus. One or two banks of SDRAM are supported.

The south bridge provides bridging between the 33 MHz PCI bus and the ISA bus. The PC/104 bus (a

compatible derivative of the ISA bus) is directly generated by the south bridge. The south bridge peripheral

and AT control functions are also fully usable by the PC/II+p board. The south bridge I/O functions include

DMA controller, Interrupt Controller, 8254 counters/timers, PS2/AT-style keyboard, PS2 mouse, IDE/ATA

Ultra-33 controller, USB root hub and 2 ports, two serial ports, and one 1284-ECP/EPP various mode parallel

port.

Please refer to the Acer Laboratories Inc. documents for the M1531B and M1543C-B1 to obtain complete

detailed descriptions of these two controllers, as listed in the section "Datasheets

" in this document.

7.3 Clock

See Section 7.21.