Specifications
PC/II+p Board Technical Reference Manual 72
MT002615 ©1999-2001, Megatel Computer Corporation
Table 38 Flat Panel Interface Signal Mapping
Mass
I/O
Pin#
Mass I/O
Pin
Name
69030
Pin
Name
Mono
SS
8-bit
Mono
DD
8-bit
Mono
DD
16-bit
Color
TFT
9/12/
16 bit
Color
TFT
18 bit
Color
TFT
24 bit
Color
TFT
HR
18/24
bit
Color STN
SS
8-bit
(x4bP)
Color
STN
SS
16-bit
(4bP)
Color
STN
DD
8-bit
(4bP)
Color
STN
DD
16-bit
(4bP)
Color
STN
DD
24-bit
B - e6
L1-FPD0
P0 P0 UD3 UD7 B0 – B0 FB0 R1 R1 UR1 UR0 UR0
B - a5
L1-FPD1
P1 P1 UD2 UD6 B1 – B1 FB1 B1 G1 UG1 UG0 UG0
B - b5
L1-FPD2
P2 P2 UD1 UD5 B2 B0 B2 FB2 G2 B1 UB1 UB0 UB0
B - c5
L1-FPD3
P3 P3 UD0 UD4 B3 B1 B3 FB3 R3 R2 UR2 UR1 LR0
B - d5
L1-FPD4
P4 P4 LD3 UD3 B4 B2 B4 SB0 B3 G2 LR1 LR0 LG0
B - e5
L1-FPD5
P5 P5 LD2 UD2 G0 B3 B5 SB1 G4 B2 LG1 LG0 LB0
B - a4
L1-FPD6
P6 P6 LD1 UD1 G1 B4 B6 SB2 R5 R3 LB1 LB0 UR1
B - b4
L1-FPD7
P7 P7 LD0 UD0 G2 B5 B7 SB3 B5 G3 LR2 LR1 UG1
B - c4
L1-FPD8
P8 – – LD7 G3 – G0 FG0 – B3 – UG1 UB1
B - d4
L1-FPD9
P9 – – LD6 G4 – G1 FG1 – R4 – UB1 LR1
B - e4
L1-FPD10
P10 – – LD5 G5 G0 G2 FG2 – G4 – UR2 LG1
B - a3
L1-FPD11
P11 – – LD4 R0 G1 G3 FG3 – B4 – UG2 LB1
B - b3
L1-FPD12
P12 – – LD3 R1 G2 G4 SG0 – R5 – LG1 UR2
B - c3
L1-FPD13
P13 – – LD2 R2 G3 G5 SG1 – G5 – LB1 UG2
B - d3
L1-FPD14
P14 – – LD1 R3 G4 G6 SG2 – B5 – LR2 UB2
B - e3
L1-FPD15
P15 – – LD0 R4 G5 G7 SG3 – R6 – LG2 LR2
B - a2
L1-FPD16
P16 – – – – – R0 FR0 – – – – LG2
B - b2
L1-FPD17
P17 – – – – – R1 FR1 – – – – LB2
B - c2
L1-FPD18
P18 – – – – R0 R2 FR2 – – – – UR3
B - d2
L1-FPD19
P19 – – – – R1 R3 FR3 – – – – UG3
B - e2
L1-FPD20
P20 – – – – R2 R4 SR0 – – – – UB3
B - b1
L1-FPD21
P21 – – – – R3 R5 SR1 – – – – LR3
B - d1
L1-FPD22
P22 – – – – R4 R6 SR2 – – – – LG3
B - e1
L1-FPD23
P23 – – – – R5 R7 SR3 – – – – LB3
B - d6
L1-SHFCLK
SHFCLK
SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK
Pixels/Clock 8 8 16 1 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3 8
NOTES
(1) The 69030 also supports panel interfaces that transfer one pixel per word, but which use both edges of SHFCLK to
transfer one pixel on each edge.
(2) The higher order output lines should be used when only 9 or 12 bits are needed from the 9/12/16-bit TFT interface, or
when only 18 bits are needed from the 18/24-bit TFT or TFT HR interfaces. The lower order bits should be left
unconnected.
(3) For STN-DD panels,
pins P0 through P35 are organized into groups corresponding to the upper and lower
parts of the panel. The names of the signals for the upper and lower parts follow a naming convention of
Uxx and Lxx, respectively.
(4) For panels that require a pair of adjacent pixels be sent with every shift clock, pins P0 through P23 are
organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels
being sent. Pins P24-P35 are unused by the PC/II+p. The names of the signals for the first and second
pixels of each such pair follow a naming convention of Fxx and Sxx, respectively.