Specifications

PC/II+p Board Technical Reference Manual 81
MT002615 ©1999-2001, Megatel Computer Corporation
8.3 Interrupt IRQ Map
Table 43 Interrupt Map
INTERRUPT REQUEST
NUMBER
SOURCE DESCRIPTION NOTES
IRQ0
M1543C TIMER 0
1
IRQ1
M1543C KEYBOARD
1
IRQ2
Cascade to Interrupt Controller 2
1
IRQ3
M1543C COM2
1
IRQ4
M1543C COM1
1
IRQ5
CS8900 ETHERNET (Optional - NOTE 2)
1,2
IRQ6
FDC
1
IRQ7
M1543C LPT1
1
IRQ8
DS1685 Real Time Clock – Timer/Alarm
1
IRQ9
IRQ10
CS8900 ETHERNET (Default)
1
M1543C USB Controller (Default) 1
IRQ11
CS8900 ETHERNET (Optional - NOTE 2) 1,2
IRQ12
M1543C PS/2 MOUSE
1
IRQ13
(Numeric Coprocessor)
1
IRQ14
M1543C IDE
1
IRQ15
NOTES
(1) Interrupt request numbers are enumerated from 0 through 15 per the conventional AT standard. Interrupt
request levels are numbered 0 through 7 in each physical 8259A interrupt controller. The interrupt
controllers are tied together through interrupt level 2 of control #1 (that is, interrupt pending requests are
presented from interrupt controller #2 to level 2 of interrupt controller #1). The physical implementation of
interrupt controllers is internal to the ACC 2089. This implementation mirrors the implementation of two
8259A controllers, so that the interface is identical to the AT standard. When an interrupt is pending for
IRQ8-IRQ15, the interrupt is in-service in both controllers, in controller #1 at level 2, and controller #2 at
level 0-7; both controllers are normally acknowledged after service completes to clear the pending
interrupt, per the standard AT standard.
(2) ETHERNET interrupts can be assigned to IRQ10, IRQ5 and IRQ11; IRQ10 is the default. Refer to
Megatel document "ETHERNET Appbook", Document number MT004702.