Speedster22i 10/40/100 Gigabit Ethernet User Guide UG029 – September 6, 2013 UG029, September 6, 2013 1
Copyright Info Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation. All other trademarks are the property of their prospective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
Table of Contents Copyright Info .................................................................................................... 2 Overview ............................................................................................................ 8 Functional Description.................................................................................... 10 Interface Signal List ........................................................................................ 12 Interface Signal Descriptions ..
Fabric FIFO Interface....................................................................................... 29 Overview .............................................................................................................................. 29 Transmit FIFO Interface Block Diagram ....................................................................................... 30 Receive FIFO Interface Block Diagram ........................................................................................
Transmit Timestamping ....................................................................................................... 58 MAC & PCS Configuration Registers ............................................................. 59 MAC & PCS Register Overview ........................................................................................... 59 Channelized MAC Registers ................................................................................................
References .....................................................................................................
Table of Figures Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram...................................................... 10 Figure 2: Interface Signal List .................................................................................................. 12 Figure 3: 10/40/100G Ethernet MAC IP Wizard ....................................................................... 22 Figure 4: Generate IP Design Files dialog box ........................................................................
Overview The hardened 10/40/100 Gigabit Ethernet controller available in Achronix Speedster22i FPGAs provides a flexible, high-performance, and power efficient networking interface. The features include: Fully integrated 10/40/100 Gigabit Ethernet MAC Designed to the IEEE Std 802.
Each PCS layer implements auto-negotiation, but does not include Parallel Detection. Parallel Detection must be implemented in user logic when the remote device does not support auto-negotiation or when auto-negotiation is disabled. When operating in 10G mode of operation, the 10G MAC can implement a configurable 10/100/1000 SGMII/1000Base-X PCS layer instead of the normal XGMII/10GBase-R PCS layer to allow operations below 10Gbps.
Functional Description FPGA Fabric Interface 10/40/100 Gigabit Ethernet Hard IP Core Physical Interface (PHY) 12 RX SerDes Lanes RX FIFO TX FIFO Physical Coding Sublayer (PCS) Media Access Controller (MAC) Configuration / Control / Statistics Physical Media 12 TX Attachment SerDes Lanes (PMA) JTAG sbus Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram On the FPGA Fabric interface side, the 10/40/100 Gigabit Ethernet MAC and PCS Core implements a flexible FIFO interface that can be connect
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Interface Signal List sys_clk ref_clk ff_clk[2:0] reset_ff_rx_clk_n[2:0] ff_tx_data[767:0] reset_ff_tx_clk_n[2:0] ff_tx_wren[11:0] ff_tx_sop[11:0] Global Signals reset_n reset_ref_clk_n ff_tx_eop[11:0] ff_tx_mod[71:0] Fabric Transmit FIFO Interface ff_tx_err[11:0] align_done[2:0] block_lock[11:0] ff_tx_crc[11:0] hi_ber[11:0] ff_tx_rdy[11:0] loc_fault[11:0] ff_tx_ovr[11:0] rem_fault[11:0] MAC/PCS Status ff_tx_id[3:0] ff_tx_ts_frm ff_tx_preamble_val ff_tx_preamble[55:0] pma_{11:0}_pd[1:0]
Interface Signal Descriptions Global Signals Table 1 – Global Signals Signal Name Mode ref_clk reset_n reset_ref_clk_n In In In reset_ts_clk_n In reset_ff_tx_clk_n[2:0] reset_ff_rx_clk_n[2:0] In In Description Reference Clock. Must be at least 652 MHz +/- 100ppm. Active low hard reset for all SerDes channels. Active low reset signal for ref_clk clock domain. Active low reset signal for ts_clk clock domain (if ts_clk is used, see below). Active low reset signal for ff_tx_clk[2:0] clock domains.
ff_rx_err[11:0] Out ff_rx_rdy[11:0] In ff_rx_afull[11:0] Out ff_rx_vlan [(12*2)-1:0] Out ff_rx_err_stat[23:0] Out ff_rx_ts[31:0] Out 000110: ff_rx_data[47:0] is valid 000111: ff_rx_data[55:0] is valid 001000: ff_rx_data[63:0] is valid (40/100G only) 001001: ff_rx_data[71:0] is valid (40/100G only) ..... .....
ff_rx_preamble_val Out ff_rx_preamble[55:0] Out SFD of the frame. Valid with ff_rx_sop. The receive timestamp ff_rx_ts[31:0] can be mapped to any segment of FIFO group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0). Receive Frame Preamble Valid Indication. Asserted (set to 1) to indicate that a valid preamble is available on pin ff_rx_preamble[55:0]. Note: Since the signal ff_rx_preamble_val is not a pulse, the application should sample ff_rx_preamble[55:0] when ff_rx_sop is set to 1. Receive Frame Preamble.
ff_tx_err[11:0] In ff_tx_crc[11:0] In ff_tx_rdy[11:0] Out ff_tx_ovr[11:0] Out ff_tx_id[3:0] In ff_tx_ts_frm In ff_tx_preamble_val In ff_tx_preamble[55:0] In 111111: ff_tx_data[503:0] is valid (100G only) Transmit Frame Error per segment. Asserted with the frame’s final data word to indicate that the transmitted frame is invalid. When ff_tx_err is asserted, the frame is transmitted to the XL/CGMII interface with a transmit error. Transmit CRC Append per segment.
pma_rx_cdr_lck2dat [11:0] Output pma_rx_iddq_n[11:0 ] Input pma_rxready[11;0] Output pma_rxstat[11:0] Output pma_sig_detect[11: 0] Output pma_synth_iddq_n[ 11:0] Input pma_synthready[11: 0] Output pma_synthstat[11:0] Output pma_tx_iddq_n[11:0 ] Input 10 – Slumber Power State (P1) - PLL is enabled. CDR and Driver are disabled. Increased power consumption 01 – Doze Power State (P0s) - Everything but transmit driver is enabled. Apprx. 20-30mW saved from the Wake state.
ff_tx_pfc_ack[11:0] Out ff_rx_pfc_xoff [11:0][ 7:0] Out Per segment Transmit Flow Control Acknowledge. Each segment provides an ACK back to the application when it samples the ff_tx_pfc_xoff inputs to indicate that a PFC/Pause control frame is about to be sent according to the provided status. 12 – 8bit bus interfaces on a per segment Receive Flow Control Status.
o_sbus_data[1:0] Out pma_[11:0]_i_sbus_ data[1:0] In pma_0_i_sbus_req In pma_0_o_sbus_ack Out pma_0_o_sbus_dat a[1:0] Out completed thru SBUS. During write it is valid for one cycle to indicate the end of the transfer. This is asserted for 4cycles to validate 8-bit data at the end of read. Contains read data for 4-cycles when o_sbus_ack is asserted. Input serial data interface for PHY PMA internal registers.
reg_ts_avail[11:0] Out counter (FRC). Used for timestamping. The value typically expresses nanoseconds within the current one second interval, hence ranging from 0 to 10^9-1. Per segment Register TS_TIMESTAMP contains new data. The pin is the direct representation of the STATUS.ts_avail register bit: It asserts when a new timestamp is stored and it becomes deasserted when writing the STATUS.ts_avail bit with ‘1’.
Implementation with ACE Software/Hardware Requirements The ACE software suite has the following system requirements: Platform: o 64 bit Linux (RHEL/Centos) o 64bit Windows 7 Memory Requirements by design size: o Minimum: 12GB o Recommended for < 100k LUTs: 16GB o Recommended for 100k – 400k LUTs: 24GB o Recommended for > 400k LUTs: 32GB Creating an Ethernet Instance The ACE design suite documentation outlines how to install the software, launch it, and setup your first project.
Figure 3: 10/40/100G Ethernet MAC IP Wizard Additionally, the user will need to select the placement of the core. The MAC cores will be located at the bottom of the device. The individual device datasheets designate the location and number of each core. Lastly, the user will chose the SerDes lane configuration that determines the positions of the chosen channels.
Figure 4: Generate IP Design Files dialog box UG029, September 6, 2013 23
FPGA Fabric Interface The fabric interface is the primary interface for the user to connect his design to the 10/40/100 Gigabit Ethernet core. The other side of the core is the dedicated PHY SerDes interface. The user accesses the Ethernet core via asynchronous transmit and receive FIFO’s. These FIFO’s have programmable watermarks that are configured by the user.
.vma file extenstion .vp or .ve file extenstion Figure 5: Simulation Flow Software simulation can be done pre-tool chain at the functional RTL level, post-synthesis at the gate level, and post-route at the Achronix technology specific level. Throughout the flow, various checkpoints can be done to insure that the design functionality is kept intact. Figure 5 shows what files are generated at each step and how they are used in the simulation framework.
Clock Distribution The clock frequency of the SerDes interface depends on the selected SerDes datapath width (synthesis option). The ACE GUI allows the user to pick one of several frequencies. The Figure below shows the system clock distribution for the 10/40/100 Gigabit Ethernet MAC and PCS Core for the 20-Bit SerDes interface.
Figure 7: Example implementation for the FIFO clock and reset multiplexers UG029, September 6, 2013 27
Reset Considerations MAC Soft Reset When the MAC control register (COMMAND_CONFIG) reset bit is written, the following functions are executed: Ongoing receive is terminated when next possible (graceful stop). A currently received frame may be written truncated to the FIFO. Transmit is disabled when next possible (graceful stop). This may lead to outgoing frame corruption (frame not terminated but transmit switches to idle immediately).
Fabric FIFO Interface Overview The following table shows the segment definition and datapath bit assignments for each configuration.
Transmit FIFO Interface Block Diagram Figure 8: Transmit FIFO Interface Block Diagram 30 UG029, September 6, 2013
Receive FIFO Interface Block Diagram Figure 9: Receive FIFO Interface Block Diagram UG029, September 6, 2013 31
Credit Handling The following figure provides an overview of the credit based application interface. Figure 10: Credit based application interface Receive Direction: FIFO to Application Internally, the receive datapath FIFO implements a credit counter which defines how many words the FIFO is allowed to deliver to the application. The credit counter is initialized by the application at startup, to the maximum burst acceptable by the application (see registers INIT_CREDIT and CREDIT_TRIGGER).
Transmit Direction: Application to FIFO On transmit, it is the responsibility of the application to monitor the ff_tx_rdy signal. The user may only transfer data to the transmit FIFO when the ff_tx_rdy signal is high. When the transmit FIFO deasserts the ff_tx_rdy signal, the user must stop sending data within the next 8 cycles or the transmit FIFO may overflow.
000001 ff_tx_data[7:0) ff_rx_data[7:0) 000010 ff_tx_data[15:0] ff_rx_data[15:0] 000011 ff_tx_data[23:0] ff_rx_data[23:0] 000100 ff_tx_data[31:0] ff_rx_data[31:0] … … 111110 ff_tx_data[495:0] ff_rx_data[495:0] 111111 ff_tx_data[503:0] ff_rx_data]503:0] Table 18 – 40G Transmit/Receive FIFO Interface Word Modulo Definition ff_tx_mod[5:0] ff_rx_mod[5:0] Valid Bytes 000000 ff_tx_data[255:0], ff_rx_data[255:0] 000001 ff_tx_data[7:0], ff_rx_data[7:0] 000010 ff_tx_data[15:0], ff_rx_data[15:0]
Table 19 – 10G Transmit/Receive FIFO Interface Word Modulo Definition ff_tx_mod[5:0] ff_rx_mod[5:0] Valid Bytes 000000 ff_tx_data[63:0], ff_rx_data[63:0] 000001 ff_tx_data[7:0], ff_rx_data[7:0] 000010 ff_tx_data[15:0], ff_rx_data[15:0] 000011 ff_tx_data[23:0], ff_rx_data[23:0] 000100 ff_tx_data[31:0], ff_rx_data[31:0] 000101 ff_tx_data[39:0], ff_rx_data[39:0] 000110 ff_tx_data[47:0], ff_rx_data[47:0] 000111 ff_tx_data[55:0], ff_rx_data[55:0] 001000 - 111111 invalid Note: Note: Only data
Table 20 – FIFO Interface Frame Format Byte Number Field 0 to 5 Destination MAC Address 6 to 11 Source MAC Address 12 to 13 Length / Type Field 14 to N Payload Data VLAN tagged frames are also supported on both transmit and receive and implement additional information (VLAN Type and Info fields).
FIFO Interface Transmit Operation The application layer drives data and controls based on the configuration mode. Note that for improved readability, the following figures only show data transfers for segment 0 in 100G mode of operation. For all other segments in other configuration modes, the corresponding signals need to be defined accordingly. The user application asserts the FIFO write enable signal (ff_tx_wren[0]) to transfer data to the MAC Core Transmit FIFO segment 0.
sys_clk ff_tx_wren[0] ff_tx_data[511:0] ff_tx_mod[5:0] ff_tx_sop[0] ff_tx_eop[0] ff_tx_err[0] Figure 12: FIFO Transmit Interface – Frame Transfer with User Application Pause By keeping the write enable signal (ff_tx_wren[0]) asserted between two consecutive frames, the user application can send back-to-back frames to the MAC Core.
The transmit FIFO interface is protected against the following invalid signaling conditions: Missing SOP: All ff_tx_wren assertions prior to ff_tx_sop assertion are ignored Missing EOP: Assertion of ff_tx_sop within a frame (i.e. no previous EOP occurred) is ignored. This error condition is latched and will cause the frame to be sent with an error indication (i.e.
sys_clk ff_rx_data[511:0] ff_rx_sop[0] ff_rx_eop[0] ff_rx_mod[5:0] ff_rx_err[0] ff_rx_vlan[1:0] ff_rx_err_stat[23:0] ff_rx_dval[0] ff_rx_rdy[0] ff_rx_preamble_val ff_rx_preamble[55:0] Figure 15: FIFO Receive Interface – Single Frame Transfer A frame transfer is stopped when the internal credit counter reaches 0. When the user application is able to accept data again, the credit update signal is asserted by the user application, which increments the internal credit counter.
When an Ethernet frame is received with an error, the frame is transmitted to the user application with the frame error signal (ff_rx_err[0]) asserted with the last word of the frame. In addition, the MAC Core provides a 24-Bit error status word (ff_rx_err_stat[23:0]) that gives an indication on the error source (see section "" for details). Note that the receive status ff_rx_err_stat[23:0] can only be mapped to any segment of FIFO group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0).
sys_clk ff_rx_data[511:0] ff_rx_sop[0] ff_rx_eop[0] ff_rx_mod[5:0] ff_rx_err[0] ff_rx_vlan[1:0] ff_rx_err_stat[23:0] ff_rx_dval[0] ff_rx_rdy[0] ff_rx_preamble_val ff_rx_preamble[55:0] Figure 18: FIFO Receive Interface – Frame Transfer with User Pause Frame Status When frame reception terminates, the MAC Core writes a status word in a dedicated internal FIFO to report information and events to the user application per frame.
Table 22 – Frame Status Word Bits Bit # Name 0 LENGTH_ERROR 1 CRC_ERROR 2 PHY_ERROR 3 FIFO_OVERFLOW 4 FAULT_SEQ 5 STACKED_VLAN 6 TRANSMIT_ERR 7 VLAN 23:8 PAYLOAD_LEN Description Set to ‘1’ if the frame has an invalid length. This can be either a too long frame (length greater than the value programmed in register FRM_LENGTH), or a frame which has a different amount of payload than specified in the frame's payload length field.
The following figure shows the relationship of the configuration values and their respective signals and levels above and below the levels.
Table 23 – FIFO Sections Configuration Register Behavior RX_FIFO_SECTIONS[15:0] Section Available: Legacy purpose only. Not available in this implementation. RX_FIFO_SECTIONS[31:16] Section Empty: If this level is reached during receive of frames, pause frames will be generated to stop the remote side from transmitting further data. If set to 0, no automatic pause frame generation is done. This function can be used only when link pause mode is enabled. It has no effect otherwise.
Table 24 – Pause Frame Format (values in hex) 1 2 3 4 5 6 7 8 55 55 55 55 55 Preamble 55 55 D5 SFD 15 16 17 00 00 19 20 21 22 00 00 00 Source Address 00 88 08 Type 18 69 70 71 72 xx xx xx CRC-32 xx 9 10 11 12 13 14 01 80 C2 00 00 01 Multicast Destination Address 23 24 00 01 Opcode 25 26 27 - 68 hi lo Quanta 00 pad (42) There is no Payload Length field found within a Pause Frame and a Pause Frame is always padded with 42 bytes (0x00).
Transmit Pause/PFC Operation In transmit direction, for each of the 12 segments, an 8-bit input vector (ff_tx_pfc_xoff[7:0]) is provided to signal the creation of PFC control frames (XOFF bit). When Link Pause Frame Mode is active, only the first input ff_tx_pfc_xoff[0] for segment n is used. After the completion of a frame, the MAC samples these inputs and determines if, depending on the current mode, a PFC or Link Pause control frame should be immediately scheduled.
A configuration option (see COMMAND_CONFIG(PAUSE_IGNORE)) allows ignoring pause frames, preventing the transmitter from being paused. When ignored the timer is not loaded and the status bit will never assert.
Serial Bus Interface Overview The Serial Bus (SBUS) Slave module is a low pin count serial interface for data transfer between the Hard IP and the FPGA Fabric. There are 13 independent SBUS interfaces. One 32-bit interface for the 10/40/100G Ethernet MAC/PCS and an additional 12 8-bit interfaces for the 12 PHY SerDes channels. The Serial bus protocol is decoded and converted into a parallel register interface called P1 port to provide access to registers by the fabric/embedded IP.
sbus_clk i_sbus_req i_sbus_data[1:0] A0,1'b0 A2,A1 A16,A15 o_sbus_ack o_sbus_data[1:0] D1,D0 D3,D2 D29,D28 D31,D30 Figure 21: Read in 32-bit Data Bus Mode sbus_clk i_sbus_req i_sbus_data[1:0] A0,1'b0 A2,A1 A16,A15 o_sbus_ack o_sbus_data[1:0] D1,D0 D3,D2 D5,D4 D7,D6 Figure 22: Read in 8-bit Data Bus Mode Write Operation For starting a write operation the i_sbus_req is asserted for 25 cycles for the case of a 32-bit write to the Ethernet SBUS interface or 13 cycles for the case of an 8-bit
PMA Management Interface Power State Descriptions The PMA supports the following 5 power States. Power state transitions are not allowed to occur, while the following events are still under way: Rate Change Data Width Change The user must ensure that any previously initiated event completes, prior to beginning a power state change. Table 27 – SerDes Power State Descriptions Power State Power Down P2 P1 P0s P0 Power State Description The power-down power state disables the lane completely.
Table 28 – Overview of PMA Behavior During the Various Power States IO Pin Signal P0 P0s P1 Power Down P2 Power State Controls and Status IRST_PCS_POR_B_A 1’b1 IRST_PCS_HARD_TXRX_Lx_B_A 1’b1 IPD_PCS_[TX,RX]_Lx_B 1’b1 IPD_PCS_SYNTH_B 1’b1 ICTL_PCS_PSTATE_Lx_[1:0] 2’b00 2’b01 2’b10 2’b11 OCTL_PCS_[TX,RX]_READY_Lx_A 1’b1 OCTL_PCS_[TX,RX]_STATUS_Lx_A 1’b1 OCTL_PCS_SYNTH_READY_A 1’b1 1’b0 OCTL_PCS_SYNTH_STATUS_A 1’b1 Transmit Lane Controls and Status TX Byte Clock OCK_PCS_TXWORD_PMA_Lx TX Byte Clock ICK_P
Power State Sequencing The following diagram demonstrates the allowed power state transitions for the PMA: Figure 25: Power State Transitioning Diagram UG029, September 6, 2013 53
Auto-Negotiation Overview Each PCS layer implements an auto-negotiation function that allows the local device to advertise supported modes of operation to another device at the remote end of an Ethernet link, and to detect corresponding operational modes the remote device may be advertising. It is used in backplane applications (Base-KR).
Control Register Bits (KXAN_CONTROL) through Next page Ability Register Bits (AN_XNP / LP_AN_XNP) for details). Usage After reset, auto-negotiation is disabled. To use it, the following steps would be typically needed (as a suggestion) for a channel.
3 Wait for base page exchange completion KXAN_STATUS 4 (opt) Perform next page exchanges AN_XNP_0..2 KXAN_STATUS 5 Configure PCS Layers BP_ETH_STATUS ACT_CTL_SEG MODE_CTL_SEG 6 Reset PCS Layers PCS_CONTROL 7 Wait for autonegotiation completion KXAN_STATUS control bit has been set the AN_XNP registers become writeable.
As soon as the PCS has established the link (block_lock asserted and align_done set accordingly for 40G and 100G mode of operation), the autonegotiation process completes and asserts the signal an_done. Note that autonegotiation cannot complete until the PCS layer has acquired a valid link. The status register should be inspected Note that, when the clock for auto-negotiation is selected (sd_tx_clk_ctrl=00), the SerDes must be configured to support autonegotiation accordingly.
IEEE 1588 Timestamping The 10 / 40 / 100 Gigabit Ethernet Channelized MAC Core supports IEEE 1588 Receive and Transmit timestamping. The timestamping support can be mapped to any segment of FIFO group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0). Receive Timestamping When a frame is received, the MAC latches the value of the timer when the frame SFD field is detected and provides the captured timestamp on ff_rx_ts[31:0]. This is done for all received frames.
Registers MAC & PCS Configuration Registers MAC & PCS Register Overview The MAC & PCS register address space is divided into 32 register pages with 256 registers each. The register pages are addressed by putting the page number/address on the serial bus interface pins. (i_sbus_req,i_sbus_data[1:0],o_sbus_data[1:0],o_sbus_ack). The following register map shows the assignment of the different register pages.
Table 31 – Core Register Map – Global Registers Address Page# 0x3000 12 0x3400 13 0x3800 14 0x3c00 15 Description 10G 40G 100G Core Configuration Registers See Core Configuration Registers on page 77 Reserved VLAN Tag Configuration Registers see VLAN Tag Configuration Registers page 78 Reserved Table 32 – Core Register Map – Channelized PCS Registers Address 0x4000 16 0x4400 17 0x4800 18 0x4c00 19 0x5000 20 0x5400 21 0x5800 22 0x5c00 23 0x6000 24 0x6400 25 0x6800 26 0x6c00
Channelized MAC Registers The Channelized MAC Registers are located on pages 0 through 11. Each segment has its own set of MAC configuration, control and status registers. The register map of each register set is identical and shown below. The following register map shows a 32-Bit register implementation. The address is given in steps of 4 to indicate the 32-bit alignment of the register space in a usual host processor memory map.
384-bit). 15:0: RX FIFO almost empty threshold 31:16: RX FIFO almost full threshold 9 24 RX_FIFO_ALMOST_F_E RO Read Only Fixed thresholds set with a Core configuration parameter. 15:0: TX FIFO almost empty threshold 31:16: TX FIFO almost full threshold 10 28 TX_FIFO_ALMOST_F_E RO 11 2C HASHTABLE_LOAD WO 12-15 30-3C reserved -- 16 40 STATUS RW 17 44 TX_IPG_LENGTH RW Read Only Fixed thresholds set with a Core configuration parameter. Hash table programming. Write only register.
20 50 CREDIT_REG RO 21 54 CL01_PAUSE_QUANTA RW 22 58 CL23_PAUSE_QUANTA RW 23 5C CL45_PAUSE_QUANTA RW 24 60 CL67_PAUSE_QUANTA RW 25 64 CL01_QUANTA_THRES H RW 26 68 CL23_QUANTA_THRES H RW 27 6C CL45_QUANTA_THRES H RW 28 70 CL67_QUANTA_THRES H RW UG029, September 6, 2013 7:0: Current credit register value (for debug purpose only). Bits 31:8 are unused and always set to ‘0’.
29 74 RX_PAUSE_STATUS RO 30 78 reserved -- 31 7C TS_TIMESTAMP RO pause condition still exists. 7:0: Status bit for software to read the pause status. One bit for each of the 8 classes. Bits 31:8 are unused and always set to ‘0’. unused Timestamp of the last frame transmitted by the Core that had the ff_tx_ts_frm signal asserted from the user application. Valid when the status bit TS_AVAIL is set to '1'.
58 E8 ifInMulticastPkts RO 60 F0 ifInBroadcastPkts RO 62 F8 ifOutErrors RO 64 100 reserved 66 108 ifOutUcastPkts RO 68 110 ifOutMulticastPkts RO 70 118 ifOutBroadcastPkts RO 72 120 etherStatsDropEvents RO 74 128 etherStatsOctets RO 76 130 etherStatsPkts RO 78 138 etherStatsUndersizePkts RO 80 140 etherStatsPkts64Octets RO 82 148 84 150 86 158 88 160 90 168 92 170 94 178 etherStatsOversizePkts RO 96 180 etherStatsJabbers RO 98 188 etherStat
110 1B8 aCBFCPAUSEFramesTra nsmitted_4 RO 112 1C0 aCBFCPAUSEFramesTra nsmitted_5 RO 114 1C8 aCBFCPAUSEFramesTra nsmitted_6 RO 116 1D0 aCBFCPAUSEFramesTra nsmitted_7 RO 118 1D8 aCBFCPAUSEFramesR eceived_0 RO 120 1E0 aCBFCPAUSEFramesR eceived_1 RO 122 1E8 aCBFCPAUSEFramesR eceived_2 RO 124 1F0 aCBFCPAUSEFramesR eceived_3 RO 126 1F8 aCBFCPAUSEFramesR eceived_4 RO 128 200 aCBFCPAUSEFramesR eceived_5 RO 130 208 aCBFCPAUSEFramesR eceived_6 RO 132 210 aCBFCPAUSEFra
Mode. See “ 224255 380 3fc reserved R(W) 10G MAC SGMII PCS Register Map” on page 71. Note: The PCS registers are 32 registers within the addresses at 0x300 .. 0x37f. They are mirrored at 0x380..0x3ff for write accesses but not for read. Hence write accesses to this register area should be omitted. COMMAND_CONFIG Register Bit Definitions Table 35 – COMMAND_CONFIG Register Description Bit# Bit Name Description 0 TX_ENA MAC Transmit Path Enable.
Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user application. If set to '0' (Reset value), pause frames are terminated and discarded within the MAC. Ignore Pause Frame Quanta. If set to '1', received pause frames are ignored by the MAC. If set to '0' (Reset value), the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame. This bit is relevant only when PFC_MODE=0. Set Source MAC Address on Transmit.
17 NO_LGTH_CHECK 18 RS_COL_CNT_EXT 19 PFC_MODE 20 PAUSE_PFC_COMP 21 RX_SFD_ANY 22 TX_FLUSH 23 to 31 reserved UG029, September 6, 2013 Disable Payload Length Check. If set to ‘0’ (Reset value), the Core checks the frame's payload length with the frame's Length/Type field. If set to ‘1’, the payload length check is disabled. If set to ‘1’, sets the reconciliation sublayer parameter col_cnt to the value set in the global register WAN_RS_COL_CNT.
STATUS Register Bit Definitions Table 36 – STATUS Register Description 70 Bit# Bit Name Type Description 0 RX_LOC_FAULT ROR Latch-High Local Fault Status. Set to '1' when the MAC detects RX Local Fault Sequences on the XL/CGMII receive interface. Reset to '0' after read and after reset. 1 RX_REM_FAULT ROR Latch-High Remote Fault Status. Set to '1' when the MAC detects RX Remote Fault Sequences on the XL/CGMII receive interface. Reset to '0' after read and after reset.
10G MAC SGMII PCS Register Map When operating in 10G mode of operation, the 10G MAC can implement a configurable 10/100/1000 SGMII/1000Base-X PCS layer instead of the normal XGMII/10GBase-R PCS layer to allow operations below 10Gbps (See 0 page 71 for further description). The following registers are accessible to control the SGMII PCS operation. The register set is found in the MAC register space from offset 0x300 onwards for each segment individually.
5 72 314 PARTNER_ABILIT Y RO 6 318 AN_EXPANSION ROR 7 31c DEVICE_NP RO 8 320 PARTNER_NP RO 9:14 324:3 38 15 33c 16 17 340 344 EXTENDED_STAT US reserved reserved RO reserved RO The PCS does not support extended status, always 0. 348 LINK_TIMER_lo RW 19 34c LINK_TIMER_hi RW 350 21:31 354:3 7C IF_MODE reserved 0 0 0 0 0 RO RO 18 20 Received ability from remote device after auto-negotiation has completed.
1000Base-X/SGMII PCS Registers Description Table 37 – (SGMII PCS) CONTROL Register Description Bit(s) Name Type Description 0 to 5 Reserved RO 6 and 13 Speed Selection RO 7 Collision Test RO 8 Duplex Mode RO 9 Restart Auto Negotiation RW 10 Isolate RW 11 Power Down RW Read only bit always set to ‘0’. Read only bits that define that the PCS only operates in Gigabit mode: Bit 13 set to ‘0’. Bit 6 set to ‘1’. Half duplex not supported by the PCS, read only bit set to ‘0’.
4 Remote Fault RO 5 Auto Negotiation Complete RO 6 7 8 9 10 11 12 13 14 15 Reserved Reserved Extended Status 100Base-T2 Half Duplex 100Base-T2 Half Duplex 10Mbps Half Duplex 10Mbps Full Duplex 100Base-X Half Duplex 100Base-X Full Duplex RO RO 100Base-T4 RO RO RO Read Only Bit always set to ‘0’. The PCS does not implement a PHY specific remote fault detection optional function.
15 NP RW the bit in the device ability advertisement register is not relevant to the operation of the autonegotiation function. The bit is typically set in the received partner ability register upon successful completion of autonegotiation. Next page capable. Set to ‘1’ to indicate next page capability.
Table 42 – (SGMII PCS) IF_MODE Register Description Bit(s) 76 Name Type 0 SGMII_ENA RW 1 USE_SGMII_AN RW 2 to 3 SGMII_SPEED RW 4 SGMII_HDUPLEX RW 5 SGMII_PCS_ENABLE RW 5 to 15 Reserved RO Description SGMII Mode Enable. When set to '0' (Reset Value), the PCS operates in standard 1000Base-X Gigabit mode, when set to '1', the PCS operates in SGMII Mode. If the bit is '0' the bits 1..4 of this register are ignored. Use the SGMII Auto-Negotiation Results to Program the PCS Speed.
Global Registers Core Configuration Registers The Core Configuration Registers are located on register page 12 (0x3000). The register map of the core configuration registers is shown below.
6 18 TS_CTL_SEG RW 7 1C STAT_CTL_SEG RW 8 20 WAN_RS_COL_ CNT RW 9-15 24-3C reserved -- 16 40 VL_INTVL RW 3:0: Timestamping support control (1 bit per segment). 0: no support for timestamping 1: support for timestamping Only segments 0, 1, 2 or 3 can be set to “1” to use the timestamping support. It is up to the user application to ensure that “1” is not set for more than 1 segment. Bits 31:4 are unused and always set to ‘0’. 3:0: Receive status vector control (1 bit per segment).
2 08 VLAN_TPID_2 RW 3 0C VLAN_TPID_3 RW 4 10 VLAN_TPID_4 RW 5 14 VLAN_TPID_5 RW 6 18 VLAN_TPID_6 RW 7 1C VLAN_TPID_7 RW 15:0: VLAN Tag TPID 2. Bits 31:16 are unused and always set to ‘0’. 15:0: VLAN Tag TPID 3. Bits 31:16 are unused and always set to ‘0’. 15:0: VLAN Tag TPID 4. Bits 31:16 are unused and always set to ‘0’. 15:0: VLAN Tag TPID 5. Bits 31:16 are unused and always set to ‘0’. 15:0: VLAN Tag TPID 6. Bits 31:16 are unused and always set to ‘0’. 15:0: VLAN Tag TPID 7.
Table 45 – PCS Register Map – General PCS Information Reg# Add. (hex) Register Name Type Description Reset [15]: Reset. 1=PCS reset (see PCS Reset on page 28), 0=normal operation. (SC) 0 00 CONTROL 1 RW 1 04 STATUS 1 RO 2 08 DEVICE ID0 RO 3 0C DEVICE ID1 RO 4 10 SPEED ABILITY RO [14]: Loopback. 1=Enable loopback (see ), 0=normal. [13]: Speed selection. (13,6)=11=bits 5:2 select speed. [12]: Reserved. Always 0, writes ignored. [11]: Low power. 1=Low power mode, 0=normal.
5 14 DEVICES IN PKG1 RO 6 18 DEVICES IN PKG2 RO 7 1C CONTROL 2 RO 8 20 STATUS 2 RO 15:7: Reserved 6: TC present 5: DTE XS present 4: PHY XS present 3: PCS present (default: 1) 2: WIS present 1: PMD/PMA present 0: Clause 22 registers present 15: Vendor specific device 2 present 14: Vendor specific device 1 present 13: Clause 22 extension present 12:0: Reserved 15:3: Reserved. Always 0, writes ignored. 2:0: PCS type selection.
Table 46 – PCS Register Map – 10G/40G/100GBASE-PCS Registers Reg# Add. (hex) Register Name Type 32 80 10/40/100G BASE-R STATUS 1 RO 33 84 10/40/100G BASE-R STATUS 2 ROR 34 88 35 8C 36 90 37 94 38 98 39 9C 40 A0 41 A4 42 A8 10G BASE-R SEED A0 10G BASE-R SEED A1 10G BASE-R SEED A2 10G BASE-R SEED A3 10G BASE-R SEED B0 10G BASE-R SEED B1 10G BASE-R SEED B2 10G BASE-R SEED B3 10/40/100G BASE-R TEST CONTROL Description Reset 15:13: Reserved 12: Receive link status.
43 AC 44 B0 45 B4 4649 B8C4 50 51 52 C8 CC D0 10/40/100G BASE-R TEST ERR CNT BER HIGH ORDER CNT ERR BLK HIGH ORDER CNT MULTI-LANE ALIGN STATUS 1 MULTI-LANE ALIGN STATUS 2 MULTI-LANE ALIGN STATUS 3 ROR Test-pattern error counter. (NR) 0 RO 15:0: Bits 21:6 of BER counter. (NR) 0 RO 15: High order counter present. Always 1, writes ignored. 14: Reserved. Always 0, writes ignored. 13:0: Bits 21:8 of errored blocks counter.
53 D4 54 89 D8 164 90 168 91 16C 92 170 93 174 94 178 95 17C 96 180 97 184 98 188 99 18C 100 190 101 194 102 198 MULTI-LANE ALIGN STATUS 4 RO 15:12: Reserved 11: Lane 19 alignment marker lock 10: Lane 18 alignment marker lock 9: Lane 17 alignment marker lock 8: Lane 16 alignment marker lock 7: Lane 15 alignment marker lock 6: Lane 14 alignment marker lock 5: Lane 13 alignment marker lock 4: Lane 12 alignment marker lock 3: Lane 11 alignment marker lock 2: Lane 10 alignment ma
BIP ERR CNT LANE 13 BIP ERR CNT LANE 14 BIP ERR CNT LANE 15 BIP ERR CNT LANE 16 BIP ERR CNT LANE 17 BIP ERR CNT LANE 18 BIP ERR CNT LANE 19 ROR 15:0: BIP error counter lane 13 (NR) Note: Bits 15:0 are reserved for 40GBASE-R. 0 ROR 15:0: BIP error counter lane 14 (NR) Note: Bits 15:0 are reserved for 40GBASE-R. 0 ROR 15:0: BIP error counter lane 15 (NR) Note: Bits 15:0 are reserved for 40GBASE-R. 0 ROR 15:0: BIP error counter lane 16 (NR) Note: Bits 15:0 are reserved for 40GBASE-R.
123 1EC LANE MAP 13 RO 124 1F0 LANE MAP 14 RO 125 1F4 LANE MAP 15 RO 126 1F8 LANE MAP 16 RO 127 1FC LANE MAP 17 RO 128 200 LANE MAP 18 RO 129 204 LANE MAP 19 RO 130 255 208 3FC 4:0: Lane mapping register for PCS lane 13 15:5: reserved Note: Bits 15:0 are reserved for 40GBASE-R. 4:0: Lane mapping register for PCS lane 14 15:5: reserved Note: Bits 15:0 are reserved for 40GBASE-R.
Auto-Negotiation Registers The Auto-Negotiation Registers are located on page 28. Each segment has its own set of 16 auto-negotiation control and status registers. The register map of each register set is identical and shown below. The following register map shows a 32-Bit register implementation. The address is given in steps of 4 to indicate the 32-bit alignment of the register space. All auto-negotiation registers are only 16-bit wide (15:0).
14 18 1C 88 ABILITY_ 2 KXAN_RE M_ ABILITY_ 0 KXAN_RE M_ ABILITY_ 1 KXAN_RE M_ ABILITY_ 2 Bit 0 is the ability word bit 32, bit 15 is the ability word bit 47. RO Received ability word from remote, bits 15:0. Bit 0 is the ability word bit 0, bit 15 is the ability word bit 15. 0x0001 RO Received ability word from remote, bits 31:16 Bit 0 is the ability word bit 16, bit 15 is the ability word bit 31.
Control Register Bits (KXAN_CONTROL) The control register controls the operation of the autonegotiation function. Table 49 – KXAN_CONTROL Register Description Bit Name Description Type 8:0 Reserved Restart AutoNegotiation Reserved AutoNegotiation Enable Bits always set to ‘0’. Self Clearing bit should be set to ‘1’ to restart the autonegotiation process. Bits always set to ‘0’. Should be set to ‘1’ to enable the auto-negotiation process.
9 Parallel Detection Fault 15:10 Reserved Error with parallel detection. When the remote device does not support autonegotiation the autonegotiation module function falls back to parallel detection only monitoring the sync indications from the PCS layers. If none or more than one sync is detected the error is asserted. Bits always set to ‘0’.
Ethernet. Following are the technology ability field encoding: Bit-15 to Bit-11 are reserved. Bit-10: 100GBASE-CR10 Bit-9: 40GBASE-CR4 Bit-8: 40GBASE-KR4 Bit-7: 10GBASE-KR Bit-6: 10GBASE-KX4 Bit-5: 1GBASE-KX Note: 10G-KX4 is not supported in this implementation and should not be set by the application. Table 53 – KXAN_ABILITY_2 / KXAN_REM_ABILITY_2 Register Description Bit(s) Name 13:0 Technology Ability (A24:A11) 15:14 FEC capability Description Reset value Bit-13 to Bit-0 are reserved.
14 Acknowledge 15 Next Page Acknowledge (Ack) is used by the auto-negotiation function to indicate that a device has successfully received its link partner’s Link Codeword. If the device does not have any Next Pages to send, the NP bit shall be set to logical zero. If a device wishes to engage in Next Page exchange, it shall set the NP bit to logical one.
PMA Registers The PMA memory contains control registers which can be grouped into two main categories: PMA Transmitter/Receiver Control – 1 page of memory. PMA Synthesizer/Common Control – 1 page of memory. The PHY module includes many control registers are a majority of them operate as override registers. Changing these register values will override local FSM control values or interface pins.
TX/RX Lane Receive Equalization Registers Table 58 – TX/RX Lane Receive Equalizer Control Registers Reg Offset [Start Bit: End Bit] (hex) 0 Register Field Name Reg Type RW/R Defau lt Value (hex) 18[2:0] RXCALEQ_DCGAIN RW 0 0 18[5:3] RXCALEQ_DFEPSTAPF3DB RW 7 0 56[3:3] RXCALEQ_LOCWREN RW 1 0 19[2:0] RXCALEQ_DFEPSTAPGAIN RW 0 0 19[6:3] RXCALEQ_DFETAP1GAIN RW 0 Reg Pg.
0 1A[7:4] 0 1B[3:0] RXCALEQ_DFETAP4GAIN RW 8 0 1B[6:4] RXCALEQ_LOFREQAGCGAIN RW 7 0 1C[7:3] RXCALEQ_HIFREQAGCCAP RW 10 UG029, September 6, 2013 RXCALEQ_DFETAP3GAIN RW 0 -4'b0000: +0mVpeak -4'b0001: +9mVpeak ... -4'b0110: +46mVpeak -4'b0111: +53mVpeak -4'b1000: -0mVpeak -4'b1001: -9mVpeak … -4'b1110: -46mVpeak -4'b1111: -53mVpeak DFE third tap gain control -4'b0000: +0mVpeak -4'b0001: +7mVpeak ... -4'b0110: +38mVpeak -4'b0111: +44mVpeak -4'b1000: -0mVpeak -4'b1001: -7mVpeak ...
Common/Synth Lane Receive Equalization Registers Table 59 – Common/Synth Lane Receive Equalizer Control Registers Reg Pg. (hex) 4 Reg Offset [Start Bit: End Bit] (hex) 53[0:0] 4 53[1:1] Reg Type RW/R Register Field Name Default Value (hex) Description RXAGC_DCCOUPLEEN RXAGC_XCOUPLEAGCE N PMA Transmit Control Registers The following sections describe registers used to control the transmit levels within the PHY.
0 17[4:3] TXDRV_SLEW RW 0 0 17[2:0] TXDRV_LEVNP1 RW 0 0 57[3:3] TXDRV_LOCWREN RW 1 TX driver Slew Rate control: 00 - 31ps 01 - 33ps 10 - 68ps 11 170ps Defines the total number of driver units allocated to the first pre-cursor (C-1) tap. The maximum value for C-1 is 3’h6 TXDRV* override enable.
4 1A[5:4] CMNTXPIPE_TXDR VSLEW_GEN3 RW 0 is not used if PCIEMODE_SEL=0. TX IO driver slew-rate look-up table entry for PCIE Gen3 If PCIEMODE_SEL=1. This value is used if PCIEMODE_SEL=0. PMA Adaptive Equalizer Registers The following sections describe registers used to configure the Adaptive Equalization within the PHY. The Receiver/Transmitter and Synthesizer control registers are split into the two sub-sections.
Common/Synth Lane Adaptive Equalizer Registers Table 63 – Table 6-14: Common/Synth Lane Adaptive Equalizer FSM Registers Reg Pg.
4 22[7:0] 23[0:0] RXEQ_FINE_RUN_ MASK RW 1FD 4 24[7:0] RXEQ_LOOKUP_CO DE_EN RW FF 4 2B[2:0] RXEQ_DCGAIN_LU P0 RW 0 4 2E[6:4] RXEQ_LOFREQAGC GAIN_LUP0 RW 7 4 2C[2:0] RXEQ_DFEPSTAPG AIN_LUP0 RW 4 4 2F[4:0] RXEQ_HIFREQAGC CAP_LUP0 RW 0 4 2C[6:3] RXEQ_DFETAP1GAI N_LUP0 RW 0 4 2D[3:0] RXEQ_DFETAP2GAI N_LUP0 RW 8 4 2D[7:4] RXEQ_DFETAP3GAI N_LUP0 RW 0 4 2E[3:0] RXEQ_DFETAP4GAI N_LUP0 RW 8 4 26[5:3] RXEQ_DFEPSTAPF 3DB_GEN2 RW 7 Equalization calibration fin
off frequency 4 2B[5:3] 4 26[2:0] 4 29[6:4] 4 27[2:0] 4 2A[4:0] 4 27[6:3] 4 28[3:0] 4 28[7:4] 4 29[3:0] UG029, September 6, 2013 RXEQ_DFEPSTAPF 3DB_LUP0 RXEQ_DCGAIN_GE N2 RXEQ_LOFREQAGC GAIN_GEN2 RXEQ_DFEPSTAPG AIN_GEN2 RXEQ_HIFREQAGC CAP_GEN2 RXEQ_DFETAP1GAI N_GEN2 RXEQ_DFETAP2GAI N_GEN2 RXEQ_DFETAP3GAI N_GEN2 RXEQ_DFETAP4GAI N_GEN2 RW 7 RW 1 RW 7 RW 0 RW 10 RW 8 RW 0 RW 8 RW 0 Equalization calibration lookup table code 0 - Pulse-shaping DFE 3dB cut-off frequency PCIe
Statistics Data Registers Overview The 10 / 40 / 100 Gigabit Ethernet Channelized MAC Core provides a set of signals per segment which can be used to implement the statistics required in IEEE 802.3 basic, mandatory and recommended Management Information packages (clause 30).
Receive Statistics Vector The Channelized MAC Core provides a Receive Statistics Vector per segment that support the statistics counters as described in the table below. Table 64 – Receive Statistics Vector - IEEE 802.
Table 66 – Receive Statistics Vector IETF RMON MIB Objects Object etherStatsDropEvents etherStatsOctets etherStatsPkts etherStatsUndersizePkts etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets etherStatsPkts1519toMaxOctets etherStatsOversizePkts etherStatsJabbers etherStatsFragments 104 Description Counts the number of dropped packets due to internal errors of the MAC Client.
Transmit Statistics Vector The Channelized MAC Core provides a Transmit Statistics Vector per segment that support the statistics counters as described in the table below. Table 67 – TX Statistics Vector - IEEE 802.3 oMacEntity and oPauseEntity Managed Objects Object Description aAlignmentErrors Frame received with an alignment error. aMACControlFramesReceived Valid control frame received. aPAUSEMACCtrlFramesReceived Valid pause frame received.
ifOutBroadcastPkts 106 the destination address set to '1' but not the broadcast address (all bits set to '1'). Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'.
References IEEE 802.3-2005 IEEE 802.3ae RFC2665, Definitions of Managed Objects for the Ethernet-like Interface Types, August 1999, www.ietf.org RFC3635, Definitions of Managed Objects for the Ethernet-like Interface Types (Update to RFC2665), September 2003, www.ietf.org RFC2863, The Interfaces Group MIB, June 2000, www.ietf.org RFC2819, Remote Network Monitoring (RMON) MIB, May 2000, www.ietf.org IEEE 802.
Revision History The following table shows the revision history for this document. 108 Date Version 4/26/2013 7/1/2013 9/6/2013 1.0 1.1 1.
