User Manual

UG029, September 6, 2013
17
10 – Slumber Power State (P1) - PLL is enabled. CDR
and Driver are disabled. Increased power consumption
01 – Doze Power State (P0s) - Everything but transmit
driver is enabled. Apprx. 20-30mW saved from the Wake
state.
00 – Wake Power State (P0) - Everything is Asserted.
Maximum power consumption.
pma_rx_cdr_lck2dat
[11:0]
Output
CDR Lock to Data status indicator
0 – CDR is locked to reference clock
1 – CDR is locked to data
pma_rx_iddq_n[11:0
]
Input
Individual Receive Lane disable/power-down control 1 –
Non-PD State - all analog circuits are enabled 0 – PD
State - all analog circuits are disabled. Analog Receiver
impedance is placed into High Impedance mode.
pma_rxready[11;0]
Output
Receive Lane Ready Status Signal:
0 – RX Lane is not ready for data transmission
1 – RX Lane is ready for data transmission
pma_rxstat[11:0]
Output
Receive Lane State Transition Status. Indicates when the
PMA has completed a requested state transition:
0 – RX Lane has not completed its state change
1 – RX Lane has completed its state change
pma_sig_detect[11:
0]
Output
Receiver Data Detection Status Signal.
0 – Indicates no/invalid data on receive pins
1 – Indicates valid data on receive pins
pma_synth_iddq_n[
11:0]
Input
Individual Synthesizer disable/power-down control
1 – Non-PD State - all analog circuits are enabled
0 – PD State - all analog circuits are disabled
pma_synthready[11:
0]
Output
SYNTH Ready Status Signal:
0 – SYNTH is not ready for data transmission
1 – SYNTH is ready for data transmission
pma_synthstat[11:0]
Output
SYNTH state transition status. Indicates when the PMA
has completed a requested state transition:
0 – SYNTH has not completed its state change
1 – SYNTH has completed its state change
pma_tx_iddq_n[11:0
]
Input
Individual Transmit Lane disable/power-down control:
1 – Non-PD State - all analog circuits are enabled
0 – PD State - all analog circuits are disabled
Priority Flow Control Interface
Table 5 – Priority Flow Control Interface
Signal Name
Mode
Description
pfc_mode[11:0]
Out
Per segment Priority Flow Control Mode. For each of the
12 segments, this signal represents the setting of the
PFC_MODE configuration register bit.
See COMMAND_CONFIG Register Bit Definitions on
page 67 for more details.
ff_tx_pfc_xoff{11:0}[
7:0]
In
Per segment transmit flow control generate. When PFC
Pause mode is enabled, for each of the 12 segments, an
8-bit input vector is used to signal the creation of PFC
control frames.
When Link Pause mode is enabled, Bit 0 of each segment
is used only.