User Manual

UG029, September 6, 2013
97
0
17[4:3]
TXDRV_SLEW
RW
0
TX driver Slew Rate control: 00
- 31ps 01 - 33ps 10 - 68ps 11 -
170ps
0
17[2:0]
TXDRV_LEVNP1
RW
0
Defines the total number of
driver units allocated to the first
pre-cursor (C-1) tap. The
maximum value for C-1 is 3’h6
0
57[3:3]
TXDRV_LOCWREN
RW
1
TXDRV* override enable.
Active Low
Common/Synth Lane Transmit Control Registers
Table 61 – Common/Synth Lane Transmit Driver Control Registers
Reg
Page
(hex)
Reg
Offset
[Start
Bit: End
Bit]
(hex)
Register Field Name
Reg
Type
RW/R
Default
Value
(hex)
Description
4
51[3:2]
TXDRV_REPLICAM
ODE
RW
2
Defines the drive strength of
transmit replica path. Used to
reduce the amount of
simultaneous switching IO noise
generated by the transmit
driver.
00 – No replica path enabled
01 – Replica path is 25% scaled
version of the main driver
10 – Replica path is 50% scaled
version of the main driver
11 – Replica path is 75% scaled
version of the main driver
4
53[2:2]
TXDRV_DCMODE
RW
4
53[3:3]
TXDRV_QPI_MODE
RW
4
17[2:0]
CMNTXPIPE_HLEV_
LUP0
RW
1
TX IO driver HLEV look-up table
entry 0
4
17[5:3]
CMNTXPIPE_HLEV_
LUP1
RW
1
TX IO driver HLEV look-up table
entry 1
4
18[2:0]
CMNTXPIPE_HLEV_
LUP2
RW
1
TX IO driver HLEV look-up table
entry 2
4
18[7:3]
CMNTXPIPE_LEVN_
LUP0
RW
19
TX IO driver LEVN look-up table
entry 0
4
19[3:0]
CMNTXPIPE_LEVN
M1_LUP0
RW
5
TX IO driver LEVNM1 look-up
table entry 0
4
1A[1:0]
CMNTXPIPE_TXDR
VSLEW_GEN1
RW
2
TX IO driver slew-rate look-up
table entry for PCIE Gen1 if
PCIEMODE_SEL=1. This value
is not used if
PCIEMODE_SEL=0.
4
1A[3:2]
CMNTXPIPE_TXDR
VSLEW_GEN2
RW
0
TX IO driver slew-rate look-up
table entry for PCIE Gen2 If
PCIEMODE_SEL=1. This value