ACX-KIT-HD1000-100G Development Kit User Guide UG034, July 1, 2014 UG034, July 1, 2014 1
Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation. All other trademarks are the property of their prospective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
Table of Contents Copyright Info......................................................................................................................... 2 List of Figures ........................................................................................................................ 6 List of Tables.......................................................................................................................... 7 Preface .....................................................................
Chapter 3 – Development Environment Setup .............................................. 17 Installing the ACE and Synopsys software and their licenses .............................................. 17 Running the software ................................................................................................................... 18 Setting up the ACX-BRD-HD1000-100G Development Board ............................................. 18 Standalone Mode ...................................................
Chapter 6 – Atmel Microcontroller ................................................................. 55 Temperature Sensing and Reporting ................................................................................... 55 Power Measurement and Reporting .................................................................................... 55 Embedded Control ...............................................................................................................
List of Figures Figure 1: ACE Development Environment............................................................................................... 12 Figure 2: ACX-BRD-HD1000-100G Development Board Picture .......................................................... 13 Figure 3: Standalone Use Mode ................................................................................................................ 14 Figure 4: In-System Use Mode ...................................................................
List of Tables Table 1: ACX-BRD-HD1000-100G Board Configuration Mode (J31) ................................................... 22 Table 2: HD1000 Configuration Mode Pins and their Connections ........................................................ 22 Table 3: HD1000 Pins and their Descriptions for Configuration ............................................................. 23 Table 4: ACX-BRD-HD1000-100G CFP Interface Pins ..........................................................................
Preface About this Guide The Achronix ACX-KIT-HD1000-100G Development Kit for the AC22IHD1000-F53C3 FPGA, delivers a practical platform for you to evaluate the Speedster22i FPGA family using the HD1000. This guide provides details on the capabilities and use of the ACX-KIT-HD1000-100G Kit. You will learn about the features that may be customized, the features that are fixed, and the tools and environment required to implement your own system designs.
Reference Documents Speedster22i FPGA Family Datasheet (DS004) ACE User Guide (UG001) Achronix Software & License User Guide (UG002) Bitporter User Guide (UG004) Conventions used in this Guide This document uses the conventions shown in the following table. Item Format Examples Command-line entries File Names GUI buttons, menus and radio buttons Variables Window and dialog box headings and sub-headings Window and dialog box names Courier bold font face Courier font face $ Open top_level_name.
Chapter 1 – ACX-KIT-HD1000-100G Overview In this chapter, you will learn the following about the ACX-KIT-HD1000-100G kit: ACX-KIT-HD1000-100G Kit Contents ACX-KIT-HD1000-100G Kit Uses ACX-BRD-HD1000-100G Development Board Features Achronix CAD Environment (ACE) Software ACX-KIT-HD1000-100G Kit Contents The Achronix ACX-KIT-HD1000-100G kit contents are as follows: Components Sub-Components ACX-BRD-HD1000-100G Development Board BitPorter Programming Pod Described below Power Supply with power cord USB ca
ACX-BRD-HD1000-100G Development Board Features FPGA Achronix 22-nm, AC22IHD1000-F53C3 Functional blocks 1 million equivalent LUTs (700k programmable LUTs + hardened IP) 86 Mbit on-chip memory (82 Mb BRAM, 4 Mb LRAM) 756 28x28 multiply/accumulate blocks 960 programmable user IOs Networking and Communications Hardened Ethernet MACs: 100GE, 40GE, 10GE 64 SerDes lanes (1 to 12.75 Gb/s) Hardened Interlaken ports, each running up to 11.
System PCI Express Gen 3 x8, for 128 Gb/s (2 x64 Gb/s - Rx, Tx) throughput USB JTAG Controller Atmel ATmega2560 Additional memories One DDR3 device QDR2+ (72Mb @ 633 MHz) Two RLDRAM3 (each 16 Mb x 36 for a total of 576 Mb @ 1066 MHz) Achronix CAD Environment (ACE) Software Achronix provides the ACE Software together with an Achronix-optimized version of Synplify-Pro from Synopsys. You will need a node-locked or floating version of the license to use the ACE Software for development.
Chapter 2 – General Description In this chapter, you will learn the following about the ACX-BRD-HD1000-100G Development Board: ACX-BRD-HD1000-100G Development Board Use Modes On-board Memory On-Board Controller Board-specific Design Issues ACX-BRD-HD1000-100G Development Board Picture The development board has a PCIe form-factor with an 8” (203.2mm) width. It also has dedicated power connectors. Figure 2 shows the ACX-BRD-HD1000-100G development board with many of the key components annotated.
Use Modes This section describes the standalone and in-system (or “plug-in”) use modes for the development board. In both modes, you must provide power to the board through the dedicated power connectors using an external power supply. Standalone Mode In this mode, the development board is placed on a bench, with control and data signals coming from the surrounding interfaces, which may include the Atmel microcontroller, DIP switches, SMAs etc. This mode is shown in Figure 3.
Power Supply PCIe Plug In Card Figure 4: In-System Use Mode On-Board Memory The development board has the following memories available for system design. A 204-pin SO-DIMM DDR3 module with 2.133 Gb/s performance. To use as the primary off-chip memory for all applications. This supplements the on-chip BRAM. To serve as a demonstration of the embedded DDR3 controller capability. A DDR3 device (2 Gb @ 1066 MHz) soldered on the board which you can use at 2.133 Gb/s performance.
IOs BRAM Fabric Take appropriate corrective action by the embedded control software. Board-Specific Design Issues The development board is optimized for Networking applications. As such, Achronix has configured the SerDes and the IOs at specific pins on the HD1000 device. You must maintain these in any changes that you make to the device as you work on your system development.
Chapter 3 – Development Environment Setup In this chapter, you will learn how to perform the following tasks: Installing the ACE and Synopsys software and their licenses Setting up the ACX-BRD-HD1000-100G Development Board Getting started Downloading a design Installing the ACE and Synopsys software and their licenses You need to perform the following steps to use the ACE Software development environment: 1. Download the required files. Typically, you will choose only ONE of the following environments: a.
Figure 5: Software Development Environment For more details on Steps 1 through 6 refer to the Achronix Software & License User Guide (UG002). Running the software You are now ready to run the software on your client machine. Run the executable file to start using ACE. For more information, please refer to the Achronix Software & License User Guide (UG002).
Standalone Board Connections Development PC (Client) USB Cable Power Supply Bitporter Pod JTAG Ribbon Cable Development Board Figure 6: Standalone Board Connections In-system Mode You need to plug the development board into an available PCIe x8 slot of the development PC. You need to leave the adjacent slot vacant to accommodate the clearance requirements for the component side of the board. Figure 7 shows the connections for this mode.
In-System Board Connections Power Supply PCIe Slot Connection Development PC (Client) USB Cable JTAG Ribbon Cable Bitporter Pod Figure 7: In-System Board Connections Getting started Power Sequencing The power sequencing on the board is preconfigured. After you connect the power supply and the power good LED (D1) is a steady red, turn on the SW4 switch. The board will automatically power up all the components in the right order.
Connect the development PC Configure the HD1000 and Run the Application There are three sources currently supported for the FPGA bitstream: 1. JTAG download through BitPorter Pod of bitstream on the development PC 2. SPI Flash 3. A Secure Digital (MicroSD) card Configuring the Board for the Appropriate Bitstream Source The board is preconfigured to accept the bitstream from the JTAG interface. Table 1 shows the shunt positions for J31 to enable the other modes. Connecting the Development PC 1.
JTAG Programming SPI Flash Programming CPU x8 Mode Programming SD CARD Figure 8: ACX-BRD-HD1000-100G Board Configuration Modes Table 1: ACX-BRD-HD1000-100G Board Configuration Mode (J31) Shunt Position Configuration Mode Bitstream Source OPEN 2&4 2&3 JTAG Serial CPU Development PC FLASH MicroSD Table 2 shows the FPGA configuration pins for the all the modes and their connections.
HD1000 (U33) Connection BYPASS_CLR_MEM CONFIG_SCRUBBING_ENABLE CONFIG_SCRUB_SINGLE_ERR CONFIG_SCRUB_MULTIPLE_ERR CORE_TESTIN1 TEMP_DIODE_N TEMP_DIODE_P CONFIG_RSTN CONFIG_STATUS CONFIG_DONE TDI TDO TMS TRSTN TCK SDI SD3 SD2 SD1 SD0 HOLDN CSN3 CSN2 CSN1 CSN0 CPU_CLK SCK START_CONFIG_STARTUP EFUSE_PROG EDM READ_STATE_ERR J18 K19 J20 M20 K20 R38 R39 J14 M16 J16 K17 K16 J19 L16 J13 L13 L14 M13 M14 N14 K13 N19 N17 J15 N20 K18 N13 K14 T14 B9 N16 SW8 TP97 TP99 TP98 U37 U96 Q8 Q9 J19 J12 J11 U29 U23 U23 UA2 S
Pin Name on HD 1000 (U33) x1 Boot from Flash (Serial Mode) - EFC CPU_CLK CONFIG_RSTN CONFIG_DONE CONFIG_STATUS CONFIG_MODESEL [2:0] CONFIG_SYSCLK_ BYPASS CONFIG_CLKSEL CPU CLOCK CPU Mode -Active-low configuration reset Open-drain configuration done output Open-drain SRAM initialization complete output Must be : ‘100’ Must be : ‘010’ Bypass configuration sys Bypass configuration sys clock : Set to ‘0’ clock : Don’t Care Select Configuration Clock : Set to ‘0’ JTAG The development PC provides the bitstr
Chapter 4 – Interfaces In this chapter you will learn about the interfaces that are available on the HD1000 FPGA and also the ones available on the development board. This guide covers details of the interfaces available on the development board. The interfaces on the HD1000 FPGA are included for completeness. Figure 9 shows the interfaces available on the HD1000 FPGA.
HD1000 FPGA Interfaces J1/J2 INTERLAKEN FMC-Serdes Group SMA 12 10 U33 FMC CLK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLL 64 204 - SO-DIMM X64 J11 USB 2.
ACX-BRD-HD1000-100G Development Board Interfaces Figure 10 shows the interfaces available on the development board.
Figure 11 below shows all of these different interfaces on the development board.
The CFP cage is directly connected to the ten bidirectional 12.5 G SerDes lanes. These are designated SerDes Bottom 8 – 17 in Figure 9. Table 4 shows the pin assignment for the CFP interface.
Signal Name SerDes No Pin on HD1000 (U33) CFP1_RX_N9 CFP1_TX_P9 CFP1_TX_N9 SERDES_CFP1_CLK1_P SERDES_CFP1_CLK1_N F28 A28 B28 M31 N31 Interlaken Interface (AirMax Connector Pair) The Interlaken interface provides a secondary high-speed datapath. You can use this to enable interoperation with other packet-processing devices such as ASICs and/or Network Processors.
Signal Name INTERLAKEN1_CLK3_N INTERLAKEN_TX_P10 INTERLAKEN_TX_N10 INTERLAKEN_TX_P11 INTERLAKEN_TX_N11 INTERLAKEN1_CLK1_P INTERLAKEN1_CLK1_N INTERLAKEN1_TX_CLK_P INTERLAKEN1_TX_CLK_N SerDes No 30 – 31 Pin on HD1000 (U33) Pin on Header (J1) BB31 BJ41 BK41 BL42 BK42 BC32 BB32 NA NA NA J4 K4 G1 H1 NA NA A1 B1 Table 6: ACX-BRD-HD1000-100G Interlaken Receiver Interface Pins Signal Name INTERLAKEN_RX_P0 INTERLAKEN_RX_N0 INTERLAKEN_RX_P1 INTERLAKEN_RX_N1 INTERLAKEN1_CLK6_P INTERLAKEN1_CLK6_N INTERLAKEN_RX_
Signal Name SerDes No INTERLAKEN1_CLK1_N INTERLAKEN1_RX_CLK_P INTERLAKEN1_RX_CLK_N Pin on HD1000 (U33) Pin on Receptacle (J2) BB32 NA NA NA A1 B1 FMC Expansion Port (HPC, J3) You can use the FMC port to add other circuitry or functionality. Banks East Centre and West North of the HD1000 provide the IOs for connections to the 400-pin SAMTEC ASP-134485-01 connector (J3) as shown in Figure 11. Table 7 shows the FMC interface pins and their connections to the HD1000.
Signal Name Pin on HD1000 (U33) FMC_TRST_N UG034, July 1, 2014 Pin on Connector (J3) D34 FMC_DP_M2C_P0 FMC_DP_M2C_N0 FMC_DP_M2C_P1 FMC_DP_M2C_N1 FMC_DP_M2C_P2 FMC_DP_M2C_N2 FMC_DP_M2C_P3 FMC_DP_M2C_N3 FMC_DP_M2C_P4 FMC_DP_M2C_N4 FMC_DP_M2C_P5 FMC_DP_M2C_N5 FMC_DP_M2C_P6 FMC_DP_M2C_N6 FMC_DP_M2C_P7 FMC_DP_M2C_N7 FMC_DP_M2C_P8 FMC_DP_M2C_N8 FMC_DP_M2C_P9 FMC_DP_M2C_N9 BF19 BG19 BE20 BF20 BF21 BG21 BE22 BF22 BF23 BG23 BE24 BF24 BF25 BG25 BE26 BF26 BF27 BG27 BE28 BF28 C7 C6 A3 A2 A7 A6 A11 A10 A15 A14 A1
Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_LA_N3 FMC_LA_P4 FMC_LA_N4 FMC_LA_P5 FMC_LA_N5 FMC_LA_P6 FMC_LA_N6 FMC_LA_P7 FMC_LA_N7 FMC_LA_P8 FMC_LA_N8 FMC_LA_P9 FMC_LA_N9 FMC_LA_P10 FMC_LA_N10 FMC_LA_P11 FMC_LA_N11 FMC_LA_P12 FMC_LA_N12 FMC_LA_P13 FMC_LA_N13 FMC_LA_P14 FMC_LA_N14 FMC_LA_P15 FMC_LA_N15 FMC_LA_P16 FMC_LA_N16 FMC_LA_CC_P17 FMC_LA_CC_N17 FMC_LA_CC_P18 FMC_LA_CC_N18 FMC_LA_P19 FMC_LA_N19 FMC_LA_P20 FMC_LA_N20 FMC_LA_P21 FMC_LA_N21 FMC_LA_P22 FMC_LA_N22 FMC_LA_P23 FMC_LA_N23 F
UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_LA_N29 FMC_LA_P30 FMC_LA_N30 FMC_LA_P31 FMC_LA_N31 FMC_LA_P32 FMC_LA_N32 FMC_LA_P33 FMC_LA_N33 BG1 BB4 BC3 BC4 BA4 AV3 BB3 AW4 AU3 G31 H34 H35 G33 G34 H37 H38 G36 G37 FMC_HA_CC_P0 FMC_HA_CC_N0 FMC_HA_CC_P1 FMC_HA_CC_N1 AY4 AY3 AN10 AN9 F4 F5 E2 E3 FMC_HA_P2 FMC_HA_N2 FMC_HA_P3 FMC_HA_N3 FMC_HA_P4 FMC_HA_N4 FMC_HA_P5 FMC_HA_N5 FMC_HA_P6 FMC_HA_N6 FMC_HA_P7 FMC_HA_N7 FMC_HA_P8 FMC_HA_N8 FMC_HA_P9 FMC_HA_N9 FMC_HA_P10 FMC_H
Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_HA_N20 FMC_HA_P21 FMC_HA_N21 FMC_HA_P22 FMC_HA_N22 FMC_HA_P23 FMC_HA_N23 AE3 AC4 AF3 AJ3 AF4 AJ4 AG4 E19 K19 K20 J21 J22 K22 K23 VREF_A_M2C AP16, AP17, AR17, AT16, AT17, AU16, AU17, AV17, AW16, AW17, AE16, AE17, AF17, AG16, AG17 AL15 (thru J532) FMC_HB_CC_P0 FMC_HB_CC_N0 AW12 AW11 K26 K25 FMC_HB_P1 FMC_HB_N1 FMC_HB_P2 FMC_HB_N2 FMC_HB_P3 FMC_HB_N3 FMC_HB_P4 FMC_HB_N4 FMC_HB_P5 FMC_HB_N5 FMC_HB_CC_P6 FMC_HB_CC_N6 FMC_HB_P7 FMC_HB_N7 FMC_HB_
Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_HB_N18 FMC_HB_P19 FMC_HB_N19 FMC_HB_P20 FMC_HB_N20 FMC_HB_P21 FMC_HB_N21 BJ8 BF8 BD8 BK8 BD7 BJ7 BE7 J36 E34 E33 F38 F37 E37 E36 VIO_B_FMC VREF_B_M2C AY16, AY17, BA17, BB16, BB17 AR15 (thru J531) K40, J39 K1 System Interfaces The ACX-BRD-HD1000-100G board has the following system interfaces: PCI Express USB JTAG PCI Express You can use the PCIe connector to plug into a development PC where the data is provided over the PCIe interface.
Signal Name PCIE_TXN4 PCIE_RXP5 PCIE_RXN5 PCIE_TXP5 PCIE_TXN5 PCIE_RXP6 PCIE_RXN6 PCIE_TXP6 PCIE_TXN6 PCIE_RXP7 PCIE_RXN7 PCIE_TXP7 PCIE_TXN7 SerDes No 5 6 7 PCIE_MAXOUT_P (SerDes Ref Clock) PCIE_MAXOUT_N (SerDes Ref Clock) Pin on HD1000 (U33) Pin on PCIe x8 Finger (J4) C15 G16 F16 A16 B16 F17 E17 B17 C17 G18 F18 A18 B18 M25 M26 J25 J26 N25 N26 K25 K26 A30 B23 B24 A25 A26 B19 B20 A21 A22 B14 B15 A16 A17 Selected using U57 USB (U54, U41) There are two USB connectors on the board, U54 and U41.
JTAG (J11) You can use the JTAG interface for communicating with the board. This interface lets you access the JTAG interface pins on the HD1000. In addition, information is transferred from the board to the development PC. The header can be seen in Figure 2. You can use this information for further debug, development or application actions. The signal pins for the 14pin are listed in Table 11. Table 11: ACX-BRD-HD1000-100G JTAG Header (J11) Pins.
Controller Interfaces The Atmel Atmega2560 (U35) controller has the following interfaces for performing several tasks on the development board. Serial interface to the USB port for communications with the development PC SD card for uploading bitstreams to the HD1000 SPI for SFLASH memory control Header for configuration HD1000 for configuration These interfaces are shown in Figure 11. Table 12 shows the relevant pins and their connections.
you with an ACE template to correctly allocate these IO pins, Bank East-South (Byte 0 – 12), for your designs. Appendix A details these pins and their connections to the SO-DIMM socket. Note: You will need to buy the memory separately. The kit does not ship with the memory. One DDR3 Device (U21) You can use the 2 Gb, Micron MT41J128M16JT-093, DDR3 memory device soldered on the board. The HD1000 drives the memory signals using dedicated GPIOs.
Signal Name Pin on HD1000 (U33) Pin on MT41J128M16JT (U21) DDR3_BA1 DDR3_BA2 DDR3_CK DDR3_CK_N DDR3_CKE DDR3_CS_N DDR3_WE_N DDR3_RAS_N DDR3_CAS_N DDR3_RST_N DDR3_ODT DDR3_LDQS0 DDR3_LDQS0_N DDR3_UDQS0 DDR3_UDQS0_N DDR3_LDM0 DDR3_UDM0 AD1 AN2 AF10 AF9 AN4 AT4 AF1 AE2 AJ2 AP4 AM3 AY2 AY1 AF13 AF14 AU2 AC14 N8 M3 J7 K7 K9 L2 L3 J3 K3 T2 K1 F3 G3 C7 B7 E7 D3 RLDRAM3 Devices (U31, U36) You can use the two 16 Mbx36 RLDRAM3 memory devices (Micron MT44K32M18RB-093) soldered on the board.
UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) RLD_DQ15 RLD_DQ16 RLD_DQ17 RLD_DQ18 RLD_DQ19 RLD_DQ20 RLD_DQ21 RLD_DQ22 RLD_DQ23 RLD_DQ24 RLD_DQ25 RLD_DQ26 RLD_DQ27 RLD_DQ28 RLD_DQ29 RLD_DQ30 RLD_DQ31 RLD_DQ32 RLD_DQ33 RLD_DQ34 RLD_DQ35 RLD_DQ36 RLD_DQ37 RLD_DQ38 RLD_DQ39 RLD_DQ40 RLD_DQ41 RLD_DQ42 RLD_DQ43 RLD_DQ44 RLD_DQ45 RLD_DQ46 RLD_DQ47 RLD_DQ48 RLD_DQ49 RLD_DQ50 RLD_DQ51 RLD_DQ52 RLD_DQ53 RLD_DQ54 RLD_DQ55 RLD_DQ56 RLD_DQ57 RLD_DQ58 RLD_DQ59 RLD_DQ60 RLD_DQ61 RLD_DQ62 RLD_DQ63 RLD_DQ64 Y4 W3
Signal Name Pin on HD1000 (U33) RLD_DQ65 RLD_DQ66 RLD_DQ67 RLD_DQ68 RLD_DQ69 RLD_DQ70 RLD_DQ71 RLD_A0 RLD_A1 RLD_A2 RLD_A3 RLD_A4 RLD_A5 RLD_A6 RLD_A7 RLD_A8 RLD_A9 RLD_A10 RLD_A11 RLD_A12 RLD_A13 RLD_A14 RLD_A15 RLD_A16 RLD_A17 RLD_A18 RLD_A19 RLD_A20 RLD_BA0 RLD_BA1 RLD_BA2 RLD_BA3 RLD_CK RLD_CK_N RLD_CS_N RLD_REF_N RLD_WE_N RLD_RESET_N RLD_QVLD0 RLD_QVLD1 RLD_QVLD2 RLD_QVLD3 RLD_TDI RLD_TDO RLD_TMS RLD_TCK RLD_DM0 RLD_DM1 RLD_QK0 RLD_QK0_N R10 M9 M10 J10 K9 L10 N10 M11 M12 K11 R11 J12 L12 N12 J11
Signal Name Pin on HD1000 (U33) RLD_QK1 RLD_QK1_N RLD_QK2 RLD_QK2_N RLD_QK3 RLD_QK3_N RLD_DK0 RLD_DK0_N RLD_DK1 RLD_DK1_N RLD_DM2 RLD_DM3 RLD_QK4 RLD_QK4_N RLD_QK5 RLD_QK5_N RLD_QK6 RLD_QK6_N RLD_QK7 RLD_QK7_N RLD_DK2 RLD_DK2_N RLD_DK3 RLD_DK3_N AA3 AA4 V9 V10 P3 P4 P11 P12 G3 G4 J1 R6 M1 M2 L5 L6 M7 M8 P9 P10 D1 D2 D5 D6 Pin on MT44K32M18RB (U31) (U36) K9 J8 D5 E6 K5 J6 D7 C7 K7 L7 B7 M7 D9 E8 K9 J8 D5 E6 K5 J6 D7 C7 K7 L7 Note: TDI, TDO, TMS and TCK (pins N10, N4, N12, and N2) are jumpered using J517
Signal Name Pin on HD1000 (U33) Pin on CY7C2565XV18 (U22) QDR2_Q7 QDR2_Q8 QDR2_Q9 QDR2_Q10 QDR2_Q11 QDR2_Q12 QDR2_Q13 QDR2_Q14 QDR2_Q15 QDR2_Q16 QDR2_Q17 QDR2_Q18 QDR2_Q19 QDR2_Q20 QDR2_Q21 QDR2_Q22 QDR2_Q23 QDR2_Q24 QDR2_Q25 QDR2_Q26 QDR2_Q27 QDR2_Q28 QDR2_Q29 QDR2_Q30 QDR2_Q31 QDR2_Q32 QDR2_Q33 QDR2_Q34 QDR2_Q35 QDR2_D35 QDR2_D34 QDR2_D33 QDR2_D32 QDR2_D31 QDR2_D30 QDR2_D29 QDR2_D28 QDR2_D27 QDR2_D26 QDR2_D25 QDR2_D24 QDR2_D23 QDR2_D22 QDR2_D21 QDR2_D20 QDR2_D19 QDR2_D18 QDR2_D17 QDR2_D16 QDR2_D15
Signal Name Pin on HD1000 (U33) Pin on CY7C2565XV18 (U22) QDR2_D12 QDR2_D11 QDR2_D10 QDR2_D9 QDR2_D8 QDR2_D7 QDR2_D6 QDR2_D5 QDR2_D4 QDR2_D3 QDR2_D2 QDR2_D1 QDR2_D0 QDR2_A0 QDR2_A1 QDR2_A2 QDR2_A3 QDR2_A4 QDR2_A5 QDR2_A6 QDR2_A7 QDR2_A8 QDR2_A9 QDR2_A10 QDR2_A11 QDR2_A12 QDR2_A13 QDR2_A14 QDR2_A15 QDR2_A16 QDR2_A17 QDR2_A18 QDR2_K QDR2_K_N QDR2_CQ_N QDR2_CQ_P QDR2_BWS0 QDR2_BWS1 QDR2_WS2 QDR2_WS3 QDR2_RPS_N QDR2_WPS_N QDR2_QVLD QDR2_ODT QDRII_TDI QDRII_TMS QDRII_TCK QDRII_TDO BG47 BJ47 BK47 BC44 AW44 BB
User Interfaces Use these interfaces to configure and drive the board, connect cables, expand I/O, review status of the board, and perform other functions related to development work. In this section, you will learn about the following. Bitporter CLI ACE GUI SMA connectors Digilent connector Jumpers LEDs Switches Figure 11 illustrates the locations of these user interfaces on the development board. Bitporter CLI Use the command line interface to configure, program and debug the HD1000.
Figure 13: ACE GUI for the Bitporter Pod For more details, refer to the “ACE User Guide (UG001)” and the “Bitporter User Guide (UG004)”. SMA Connectors There are ten SMA connectors on the board as shown in Figure 11. These are connected to the HD1000 as shown in Table 16. You can use these for various clocking functions.
Connector Signal Pin on HD1000 (U33) SMA PAD0_CLK_BANK_SE PAD1_CLK_BANK_SE N38 P37 Function J49 J50 Digilent connector (J29) You can use the Digilent connector (J29) to expand the functionality of the board. This is a standard right-angle 1x6 Molex connector. Figure 11 shows the connector and Table 17 shows the connections to the relevant pins on the HD1000.
HD1000 (U33) CONFIG_CLKSEL PROGRAM_ENABLE0 PROGRAM_ENABLE1 STAP_SEL UG034, July 1, 2014 Switch (SW7) M17 K15 M19 L19 CFG_CLKSL PRG_EN0 PRG_EN1 STAP_SEL 5, 12 6, 11 7, 10 8, 9 51
Chapter 5 – Clocking In this chapter you will learn about the crystals and oscillators on the board. These provide the inputs to the clock synthesizers or the HD1000 clock banks to generate all the frequencies required to implement the system level functions. You can also drive some of the clocks from external sources using the relevant interface or through the SMA connectors. Table 19 shows all the crystals on the board and their functions.
Table 20: Sample DIP Switch Settings to Generate Desired Synthesizer Output Clocks M5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M Counter (SW12) M4 M3 M2 M1 M0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 M Value 20 21 22 23 24 25 20 21 22 23 24 21 22 23 24 25 21 22 23 24 25 20
Signal Name Pin on HD1000 (U33) Pin on ICS853310 (U72) INTERLAKEN1_CLK2_P INTERLAKEN1_CLK2_N INTERLAKEN1_CLK3_P INTERLAKEN1_CLK3_N INTERLAKEN1_CLK4_P INTERLAKEN1_CLK4_N INTERLAKEN1_CLK5_P INTERLAKEN1_CLK5_N INTERLAKEN1_CLK6_P INTERLAKEN1_CLK6_N AY32 AW32 BC31 BB31 AY31 AW31 BC29 BB29 BC28 BB28 20 19 18 17 16 14 13 12 11 10 The 16 MHz oscillator (Y4) provides the clock to the microcontroller (U35). The 25 MHz (Y7) crystal provides the input to the IDT 9FG430 Frequency Timing Generator (U101).
Chapter 6 – Atmel Microcontroller You can use the on-board, Atmel Atmega2560 microcontroller (MCU) for monitoring and control functions. Temperature sensing and reporting Power measurement and reporting Embedded control Temperature Sensing and Reporting The MCU monitors the temperature of the HD1000 using the Maxim device, MAX6642 (U37). This device asserts an alarm signal when the HD1000 operating temperature increases above the set threshold.
Configuring the HD1000 through Serial or CPU mode Responding to over-temperature/over-current alarm Driving status LEDs Interfacing to the Development PC Interfacing to the MicroSD socket Table 24 shows the MCU pins and their connections. For more information about the Atmega2560, refer to the datasheet available at www.atmel.com.
Appendix A – HD1000 Pins and their connections to the SO-DIMM Socket Table 25: ACX-BRD-HD1000-100G SO-DIMM Socket Pins and their Connections Category Bank East South 1 (Byte 0) Bank East South 1 (Byte 1) Bank East South 1 (Byte 2) Bank East South 1 (Byte 3) UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) SODIMM_DQ0 SODIMM_DQ1 SODIMM_DQ2 SODIMM_DQ3 SODIMM_DQ4 SODIMM_DQ5 SODIMM_DQ6 SODIMM_DQ7 SODIMM_DM0 SODIMM_DQS0 SODIMM_DQS_N0 SODIMM_DQ8 SODIMM_DQ9 SODIMM_DQ10 SODIM
Category Bank East South 3 (Byte 8) Bank East South 3 (Byte 9) Bank East South 3 (Byte 10) Bank East South 3 (Byte 11) Bank East South 2 (Byte 4) Bank East South 2 58 Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) SODIMM_DQ31 SODIMM_DM3 SODIMM_DQS3 SODIMM_DQS_N3 SODIMM_DQ32 SODIMM_DQ33 SODIMM_DQ34 SODIMM_DQ35 SODIMM_DQ36 SODIMM_DQ37 SODIMM_DQ38 SODIMM_DQ39 SODIMM_DM4 SODIMM_DQS4 SODIMM_DQS_N4 SODIMM_DQ40 SODIMM_DQ41 SODIMM_DQ42 SODIMM_DQ43 SODIMM_DQ44 SODIMM_DQ45 SODIMM_DQ46 SODIMM_DQ4
Category Signal Name (Byte 5) SODIMM_CSN1 SODIMM_CKE0 SODIMM_CKE1 SODIMM_ODT0 SODIMM_ODT1 SODIMM_RESET_N SODIMM_EVENT_N SODIMM_A14 SODIMM_CLK1 SODIMM_CLK_N1 SODIMM_A0 SODIMM_A1 SODIMM_A2 SODIMM_A3 SODIMM_A4 SODIMM_A5 SODIMM_A6 SODIMM_A7 SODIMM_A8 SODIMM_A9 SODIMM_A10 SODIMM_A11 SODIMM_A12 SODIMM_A13 SODIMM_A14 SODIMM_BA0 SODIMM_BA1 SODIMM_BA2 SODIMM_WE_N SODIMM_CAS_N SODIMM_RAS_N SODIMM_SA0 SODIMM_SA1 DDR3_I2C_SCL DDR3_I2C_SDA VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD
Category Reference Voltages Ground 60 Signal Name VDD_17 VDD_18 VTT_1 VTT_2 VREFCA VREFDQ VDDSPD VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) 123 124 203 204 126 1 199 2 3 8 9 13 14 19 20 25 26 31 32 37 3
Category Signal Name VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) 178 179 184 185 189 190 195 196 Note: The pins called out as “Miscellaneous Signals” are used for communications with I 2C master.
Appendix B – LEDs, Buttons, Jumpers, and Switches The following tables list the various LEDs, buttons, jumpers, and switches on the board. You can use these for configuration, status indication, or reset.
Jumpers Table 28: Jumpers and their Functions Jumper Implementation Connected Pins Surface Mount Resistor None Function JTAG J54 1&2 2&3 J17 Surface Mount Resistor Surface Mount Resistor J19 Surface Mount Resistor 2&3 3&4 J32 4-Pin Jumper 1&2 None 2&3 3&4 Surface Mount Resistor J39 4-Pin Jumper 1&2 None 2&3 3&4 UG034, July 1, 2014 Surface Mount Resistor for FPGA TDI-TDO JTAG Chain connectivity Connects RLDRAM_TMS Selects RLDRAM_TDI to TDI connection RLDRAM_TDI to RLDRAM_TDO, bypassi
Jumper Implementation J27 4-Pin Jumper Connected Pins 1&2 None Function Connects QDRII_TMS Selects QDRII_TDI to TDI connection QDRII_TDI to QDRII_TDO, bypassing QDRII TDO to QDRII_TDO connection for QDRII TDI-TDO JTAG Chain connectivity 1&2 1&3 1 & 4* X1 X4 X8 PCIe data width 1 & 2* Selects HD1000 2&3 Selects Microcontroller 1 & 2* Selects HD1000 2&3 Selects Microcontroller 1 & 2* Selects HD1000 2&3 Selects Microcontroller 1 & 2* Selects HD1000 2&3 Selects Microcontroller 1&2 2&3 3
Jumper Implementation Connected Pins 1&2 2&3 Function Selects VREF_A_M2C Selects ADJ _FMC for pin AE15 (U33) RESET J37 Surface Mount Resistor None 1&2 Part of microcontroller reset circuitry Configuration J34 Surface Mount Resistor None 1 & 2* 2&3 J31 4-Pin Jumper Open 1&2 2&3 2&4 Selects OE_FPGA_HEADER Selects OE_FPGA_BUF Selects JTAG programming from Development PC Selects EPROM programming Selects CPU programming from MicroSD Card Selects Serial programming from Flash to drive OE_L_UNI_LV
Jumper Implementation Connected Pins J46 Surface Mount Resistor 1 Function Selects VDDL_REG 0.75V-1.2V 2 3 4 Surface Mount Resistor J51 0.75V 1.0V 1.2V 1 Selects VDD_BRAM_FB 2 3 4 Surface Mount Resistor J53 0.75V-1.2V 0.75V 1.0V 1.2V None 1&2 2&3 Selects V3P3 Selects VBB_INLKN1 Note: ‘*’ denotes default setting.
Switch No Position SW14 SW5 SW2 SW1 SW6 SW10 SW8 SW9 SW11 1 2 1 2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 1 2 3 4 1 2 3 Function Clock select input Clock select input Clock select input Clock select input PLL/Bypass mode Output divider value Output divider value Output divider value Output divider value Output divider value Output divider value Clock divider input Clock divider input Clock divider input Clock divider input Clock divider input Clock divider input Clock d
Appendix C – Troubleshooting Q: Where can I find more information about this kit and the HD1000? A: Visit the Achronix website www.achronix.com to get more information about our products and supporting documentation.
Appendix D – Revision History The following table lists the revision history of this document. UG034, July 1, 2014 Date Version 04/05/2013 04/15/2013 04/24/2013 1.0 1.1 1.2 04/29/2013 1.3 07/16/2013 1.4 08/17/2013 1.5 09/27/2013 1.6 12/02/2013 03/02/2014 03/11/2014 1.7 1.8 1.9 06/23/2014 1.10 07/01/2014 1.11 Revisions Initial Achronix release. Corrected links. Updated crystal oscillator component numbers. Put in more component numbers in figures. Updated Interlaken tables.
