User Manual
Table Of Contents
Figure 3: RX Clock Domains
hs
_if
per_lane_
rx
rx
_destriping
clk
serDes
IIPC Core
hs_
if
per
_
lane
_
rx
serDes
hs
_
if
per_lane_rx
serDes
hs_if
per
_lane
_
rx
serDes
hs
_
if
per_
lane_rx
serDes
hs_if
per
_lane_
rx
serDes
hs_
if
per_lane
_rx
serDes
hs_if
per
_lane_
rx
serDes
hs_
if
per
_lane
_
rx
serDes
hs_
if
per
_lane_rx
serDes
hs_if
per_
lane_rx
serDes
hs_
if
per
_lane_rx
serDes
Interface to user logic in the FPGA Core
rx_serdes_clk[0]
rx_
serdes
_clk
[
1
]
rx_serdes_clk[2]
rx
_
serdes_
clk[
3
]
rx
_serdes_
clk[
4]
rx
_serdes_
clk[
5]
rx
_serdes_
clk[6
]
rx
_serdes_
clk[7]
rx_
serdes
_clk[
8]
rx
_serdes
_clk
[9]
rx
_serdes
_
clk[10]
rx
_
serdes_
clk[11
]
UG032, May 15, 2014
13