Speedster22i SerDes User Guide UG028 (v2.
Table of Contents List of Figures .................................................................................................................................... 5 List of Tables ..................................................................................................................................... 6 Overview ............................................................................................................ 7 Physical Media Attachment (PMA) .......................................
The deskew module can work in three modes: .............................................................................................. 26 Standards Supported by Deskew Module ...................................................................................................... 27 Elastic FIFO (Elastic Buffer) ............................................................................................................. 27 EFIFO Standards and Skip Characters ................................................
RX PCS Settings ............................................................................................................................................. 64 RX PCS Symbol Alignment............................................................................................................................. 66 TX PCS Settings .............................................................................................................................................
List of Figures Figure 1: Location of SerDes Lanes ...................................................................................................................................... 11 Figure 2: SerDes Architecture................................................................................................................................................ 12 Figure 3: PMA Architecture .......................................................................................................................
List of Tables Table 1: SerDes Standards........................................................................................................................................................ 9 Table 2: Symbol Slip Paramaters........................................................................................................................................... 27 Table 3: Shift Limit ..........................................................................................................................
Chapter 1 – SerDes Architecture Overview Achronix Speedster22i FPGAs provide very high core fabric and I/O performance which exceeds the system bandwidth requirements of various high end applications. The Speedster22i device family supports up to 64 full-duplex SerDes lanes, each supporting up to 11.3 Gbps data rate. The Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sub-blocks together comprise a single SerDes block.
o Programmable spread spectrum generation o Support for 16-bit fractional multiplication factors o Programmable spread spectrum clocking o Support for fast lock mode for EPON/GPON • On-chip scope in the receiver for measuring eye width, eye height and BER for the incoming signal • On-chip calibrated 100 ohm termination • Transparent calibration engine to compensate for PVT variation Clocking • Support for external reference clock from 50 MHz – 300 MHz • Support for recovered reference clock
Major standards supported Table 1: SerDes Standards Standards PCI Express Gigabit Ethernet 10 Gigabit Ethernet Variation Data Rate(s) Gen1 2.5 Gbps Gen 2 5.0 Gbps Gen 3 8.0 Gbps 1000BASE-CX 1.25 Gbps SGMII 1.25 Gbps XAUI (802.3ae) 3.125 Gbps XFI 10.3125 Gbps 10GBASE-R (802.3ae) 10.3125 Gbps 10GBase-KR (802.3ae) XLAUI/CAUI (802.3ae) Interlaken OIF Fiber Channel SONET UG028, July 1, 2014 10.3125 Gbps 10.3125 Gbps -- 3.125 – 10.3125 Gbps SPI5 3.125 Gbps SFI4.2 3.
Standards Variation 4.8 Gbps QPI SATA SAS Serial Rapid I/O Data Rate(s) 6.4 Gbps SATA-1 1.5 Gbps SATA-2 3.0 Gbps SATA-3 6.0 Gbps SAS-1 3.0 Gbps SAS-2 6.0 Gbps SAS-3 12.0 Gbps Gen1 1.25 Gbps Gen1 2.5 Gbps Gen1 3.125 Gbps Gen2 5.0 Gbps Gen2 6.125 Gbps 1.25 Gbps E-PON 802.3av 2.5 Gbps 10 Gbps 1.25 Gbps GPON -- 2.5 Gbps 10 Gbps InfiniBand SDR 2.5 Gbps DDR 5.0 Gbps QDR 10.0 Gbps JESD204B 10 Up to 12.5 Gbps CPRI -- 614.4 – 9830.
SerDes Placement The Speedster22i device supports up to sixty-four (64), 11.3 Gbps SerDes lanes. Each side (Top and Bottom) has thirty-two (32), 11.3 Gbps SerDes. The lanes are organized by channel based, and are placed as illustrated in “Figure 1: Location of SerDes Lanes ” below.
SerDes Architecture Overview The SerDes has an independent lane architecture. Each lane has a Physical Media Attachment (PMA), Synthesizer (Transmit PLL), Clock and Data Recovery (CDR) and Physical Coding Sublayer (PCS). The Receiver PMA and Transmitter PMA block diagrams are shown in “Figure 2: SerDes Architecture” below.
Physical Media Attachment (PMA) The PMA architecture is shown in “Figure 3: PMA Architecture” below. Figure 3: PMA Architecture The PMA consists three major blocks: 1. Common 2. Receiver/Transmitter (RX/TX) 3. Digital PMA (DPMA) 1. Common The common block consists of the following circuits: • Reference clock: This circuit performs reference clock buffering and division before feeding it to the Synthesizer.
2.
Figure 5: Receiver Architecture UG028, July 1, 2014 15
PCS Blocks in the Transmitter (TX) This section presents the transmitter (TX) data path within a PCS. The key blocks within the SerDes transmitter are: • Encoder: Encodes the data for transmission line. Primary goal is to ensure DC balance by eliminating long sequence of 1’s or 0’s. • Polarity Bit Reversal (PBR): Inverts the polarity of data and ordering of data to be transmitted. The building block for the SerDes IP is the 1 lane configuration.
Polarity and Bit Inversion – 10/20 bit Operation When operating in 10bit/20bit mode, the bit order within each 10-bit word can be inverted. This is illustrated in “Figure 7: 20 bit Order Reversal”. Effectively the most significant bit of the least significant byte is transmitted first (i.e. bit 9 of byte 0 is transmitted first). Figure 7: 20 bit Order Reversal When the word order is reversed in 20-bit mode, the most significant byte (byte 1) is swapped with the least significant byte (byte 0).
Polarity and Bit Inversion – 8/16 bit Operation When the polarity is inverted in 8bit/16bits mode, only bits [17:10] and [7:0] are inverted, bits [19:18] and [9:8] are not inverted. This is illustrated in “Figure 9: Polarity Inversion (16-bit Word)”. Figure 9: Polarity Inversion (16-bit Word) When the bit order is inverted in 8bit/16bit mode, bits [7:0] of byte 0 are swapped while bits [9:8] are not swapped. Similarly bits [17:10] of byte 1 are swapped.
Figure 11: Word Order Inversion (16-bit Word) UG028, July 1, 2014 19
Interface Encapsulation This block encapsulates the protocols supported by the SerDes in Achronix FPGA. The user may refer to Section – “PCS Interface” for details on the protocols supported. It may be noted again that the SerDes configured in Generic mode supports only 8b/10b encoding. 8b/10b Encoder The 8b/10b encoder generates 10-bit code groups from 8-bit data and a 1-bit control input. It uses the code group mapping specified in IEEE 802.3 clause 36.
The input disparity for the 6 bit block is based on the disparity of previous word’s 4 bit block while the disparity for the 4 bit block is the disparity of the current word’s 6 bit block. This is illustrated in “Figure 12: 8b/10b Encoding Process”.
PCS Blocks in the Receiver (RX) This chapter describes the PCS components on the receiver data path. The functional block diagram of the receiver is shown in “Figure 13: - PCS Receive Block Overview”. The key blocks in the RX-PCS include: • Transition Density Checker (TDC): Generates a trigger bit when the number of consecutive 1’s or 0’s reaches a pre-defined value. • Polarity Bit Reversal (PBR): Inverts data, swaps byte ordering and reverses bitordering, if used on the TX data path.
Equation 1: 𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 = (𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑃𝑟𝑜𝑔𝑟𝑎𝑚𝑚𝑒𝑑 ∗ 𝑠𝑐𝑎𝑙𝑖𝑛𝑔) + ℎ𝑎𝑙𝑓 𝑡ℎ𝑒 𝑤𝑖𝑑𝑡ℎ 𝑜𝑓 𝑑𝑎𝑡𝑎 − 𝑝𝑎𝑡ℎ The assert signal from Transition Density Checker can be taken to fabric. Note: Any bit transition would cause the counter to clear and the count to restart. Polarity Bit Reversal (PBR) The polarity bit reversal block is used to invert data, swap byte ordering, and reverse bitordering.
Modes of Operation Manual Mode: In manual alignment mode, the symbol alignment will attempt to identify a pre-configured pattern and lock to the incoming de-serialized data-stream from the output of the PMA or phase picking block. The alignment operation is triggered by the user logic in the FPGA on the rising edge of RX_com_det_en. The symbol alignment block then searches for the preconfigured alignment pattern with or without trailing sequence pattern. Fabric will wait for the lock status.
Deskew FIFO The deskew block provides support for standards which require multiple lane bonding and de-skewing of received data across multiple lanes. Lane bonding is required when the users want to transmit data faster than is possible by using one serial link (lane). In such case, the data is received must be aligned across the lanes. Deskew module within the SerDes takes care of this.
Functional Description The de-skew block uses a deskew FIFO on each lane. The writes to the deskew FIFO are performed in the recovered clock domain for each lane. The read side of the deskew FIFO is clocked by the clock from the initiator lane. The lanes are categorized as initiator and followers. Any lane can be an initiator and skew is always calculated between the initiator and each of follower lanes.
Symbol slip mode: The deskew module does not actively remove skew across lanes. Each lane is controlled by the fabric. Fabric continuously monitors incoming data and employ a mechanism to find out the skew across lanes. Based on the calculation, it instructs each lane to adjust the read pointer of FIFO. The read pointer can be incremented once by 0, 1 or 2 based on the combination of rising edges on symbol_slip_up and symbol_slip_dn.
EFIFO Standards and Skip Characters PCIe Gen3: To support PCIe Gen3, 4-bytes of skip are added at byte positions 4-7 from the sync header associated with the skip ordered set. Skip removal happens from bytes 0-3 from the sync header associated with the skip ordered set. Due to this particular rule of removal, sync header and receive start block indications are delayed by 4-bytes.
EFIFO Operation “Figure 15: EFIFO SKP Addition/Removal” illustrates the process of SKP addition/removal. Figure 15: EFIFO SKP Addition/Removal In “Figure 15: EFIFO SKP Addition/Removal” upon reset, the difference between the read and write counters is equal to fifo_mid (half the size of the buffer; default 16).
“Figure 16: EFIFO SKP Addition/Removal: PCIE, GigE (802.3) and XAUI (802.3)” illustrates SKP additions and removals for PCIe, GigE (802.3), and XAUI (802.3ae). Note that in the figure, data_i and data_o are not actually aligned, they are merely depicted so for clarity. Figure 16: EFIFO SKP Addition/Removal: PCIE, GigE (802.3) and XAUI (802.
Overflow/Underflow If the difference between the write and read counters is greater than fifo_full, then the overflow signal is asserted. If the difference between the write and read counters is less than fifo_empty, then the underflow signal is asserted. 8b/10b Decoder The 8b/10b decoder generates 8-bit code groups and 1-bit control from 10-bit encoded (received) data. It uses the code group mapping specified in IEEE 802.3 clause 36.
the 20-bit mode of operation, the most significant 20-bits of data are placed on bits 19:0 of the barrel shifter and the least significant 20-bits are discarded. The 6-bit select control can select a range of active bits, from [19:0] (for a select value of 0x00) to [82:63] (for a select value of 0x3F). “Table 4: List of Important Interface Signals for bit slider”, provides a list of important interface signals used for bit slider.
PCS Interface The PCS interface provides the general interface between the PCS and the core fabric. The PCS supports the following interfaces: • Gigabit Ethernet Interface • XAUI • PIPE Interface • 10G Ethernet Interface Gigabit Ethernet Interface The PCS in Achronix SerDes supports 10G Ethernet, compliant with section 36, 37 of IEEE 802.3. Functionalities implemented are PCS transmit, carrier sense, synchronization, receive, and auto-negotiation.
XAUI The PCS supports XAUI compliant with section 48 of IEEE 802.3. The Protocol block implements the Transmit and Receive state machines as per Figures 48-6 and 48-9 of IEEE 802.3. For synchronization, de-skew and clock compensation operations, symbol alignment, de-skew and elastic buffers in PCS are used. 8b/10b encoders and decoders are used for handling 10-bit code groups. When communicating with the XGMII (fabric side), the PCS uses in each direction 32 data signals and 4 control signals.
The 128b/130b encoder is disabled on power up, and enabled when the rate bits coming from the MAC are configured to 2’b10. The PCS layer support for PCIe gen3 also includes glue logic to switch the PMA data width to 16-bit mode and programming final rate bits for PCIe gen3 operation. “Table 5: PIPE Interface Paramaters” shows various supported combinations of clocking speeds and data-widths. Table 5: PIPE Interface Paramaters UG028, July 1, 2014 PCIe Mode PCLK PMA Data Width 2.5 Gbps Gen1 2.
Clocking “Figure 17: SerDes RX and TX clocks” gives an overview of the clocks inside the SerDes. The PMA of a SerDes lane generates two clocks, a TX word clock synthesized from the reference clock, and an RX word clock recovered from the incoming serial data stream. The frequency of these clocks is the data rate divided by the word width. For instance, a 10Gbps data rate with 20 bit data width results in a 500MHz clock.
Although each lane has its own clock output pins to the fabric, with lane bonding these are all just route-throughs of the master clock: regardless of which clock output pins are used, only one clock net is routed inside the fabric. This is an important feature of Lane Bonding, because the FPGA fabric can only accommodate a limited number of distinct clocks. Lane Bonding divides the number of distinct clocks inside the core by the size of the group.
Debug and Test The SerDes comes integrated with a wide range of debug and test features for excellent coverage. The following features are provided: • Seven different loopback modes • Pseudo-Random Binary Sequence (PRBS) pattern generators and checkers on PMA and PCS. • User-defined pattern generator and checker in PMA and PCS. Loopback Modes The SerDes supports up to seven different loopback modes. The loopback modes can be divided as PMA loopback and PCS loopback.
PMA loopback modes: Figure 18: PMA Loopback Modes PCS loopback modes: Figure 19: Looback modes Please refer “Dynamic Read/Write of SerDes Registers (Through SBUS)” section to set different loopback modes in the user design using ACE macro ACX_SERDES_REG_CTRL UG028, July 1, 2014 39
PMA Test Pattern Generator The PMA supports a built in transmit data pattern generator that can be used for transmit characterization. The test pattern generator can transmit PRBS patterns and user defined patterns.
The transmit pattern generator can optionally transmit user defined patterns instead of PRBS patterns, configured through the control registers. Two sets of user defined patterns (up to 40-bits each) can be configured. The user can decide to send a single 40-bit pattern or two alternate 40-bit patterns.
Latency This section presents the worst case latency for PMA and PCS blocks. PMA Latency The following equation calculates the worst-case latency for the Tx-datapth assuming the case of first word in and last bit out: 𝑇𝑥𝑤𝑜𝑟𝑠𝑡 = 𝐴𝑛𝑎𝑙𝑜𝑔_𝑙𝑎𝑡𝑒𝑛𝑐𝑦 + 2.5 ∗ 𝑑𝑎𝑡𝑎𝑏𝑢𝑠_𝑤𝑖𝑑𝑡ℎ ∗ 𝑈𝐼 + (𝑑𝑎𝑡𝑎𝑏𝑢𝑠_𝑤𝑖𝑑𝑡ℎ − 1) ∗ 𝑈𝐼 + 500𝑝𝑠, where analog latency is explained below and 500 ps accounts for internal analog delay and digital clock newtowrk latency.
“Table 9: Latency across the PCS blocks” presents the latency experienced by datapath in these two modes. The worst case latency is presented in in “Figure 20 Worst-case latency across PMA and PCS” Table 9: Latency across the PCS blocks # PCS Module 6. Polarity bit reversal symbol swap 0 8b/10b Encoder Polarity bit reversal symbol swap 1 8b/10b Decoder Symbol Alignment Module Deskew Module 7. EFIFO Module 8. Other 1. 2. 3. 4. 5.
Figure 20 Worst-case latency across PMA and PCS (in terms of clock-cycles) 44 UG028, July 1, 2014
Configurations Supported Table 10: Supported Transmitter (TX) Features PCI Express 10 Gigabit Ethernet Interlaken Numb er of Lanes Suggested Reference Clock (MHz) Parallel Data Width (Bits) Gen1 2.5 1/4/8 100 8/16 Gen2 5.0 1/4/8 100 8/16 Gen3 8.0 1/4/8 100 16 Variation Standard Gigabit Ethernet Data Rates (Gbps) Encoder PBR Out-ofBand 8b/10b 8b/10b 128b/130 b Yes Beacon Yes Beacon Yes Beacon GigE (1000BASECX) SGMII XAUI 1.25 1 125 8 8b/10b Yes No 1.25 3.
Standard Data Rates (Gbps) Numb er of Lanes OC-24 1.244 1 OC-48 2.48832 1 OC-192 9.95 1 SATA-1 1.5 1 SATA-2 3.0 SATA-3 SAS-1 SAS-2 Variation Suggested Reference Clock (MHz) 622.08, 155.52 622.08, 155.52 622.08, 155.52 Parallel Data Width (Bits) Encoder PBR Out-ofBand 8/10 No Yes No 8/10 No Yes No 20 No Yes No Variable 8/10 No Yes 1 Variable 8/10/16/20 No Yes 6.0 1 Variable 16/20 No Yes 1.5/3.0 1 Variable 8/10/16/20 No Yes 6.
Table 11: Supported Receiver (RX) Features PBR Transition Density Checker Clock Compen sation (EFIFO) Lane Deskew Decoder Bit Slide r Standard Variations Data Rates (Gbps) PCI Express Gen1 2.5 Yes Yes Yes Yes No 8b/10b No Gen2 5.0 Yes Yes Yes Yes No 8b/10b No Gen3 8.0 Yes Yes Yes No 128b/13 0b No (1000BaseCX) 1.25 Yes Yes Yes Yes No 8b/10b No SGMII 1.25 Yes Yes Yes Yes No 8b/10b No XAUI 3.125 Yes Yes Yes Yes Yes 8b/10b No XFI 10GBASE-R (802.
Symbol Align Clock Compen sation (EFIFO) Lane Deskew Decoder Bit Slide r Yes Yes Yes 8b/10b No Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No Variations SONET 10GFC OC-12 OC-24 OC-48 OC-192 SATA-1 10.52 0.622 1.244 2.48832 9.95 1.5 Yes Yes Yes Yes Yes SATA-2 3.0 Yes No SATA-3 6.0 Yes No No No No SAS-1 1.5/3.0 Yes No No No No SAS-2 6.0 Yes No No No No SAS-3 12.
Design Flow: Creating a SerDes Design In this chapter, step-by-step instructions for creating a SerDes design are presented: 1. Generation of SerDes wrapper using ACE GUI 2. Design of top-level RTL to instantiate the SerDes wrapper created in step 1. 3. Definition of placement and timing for the SerDes. 4. Design guidelines This chapter starts with a simple design and presents step-by-step instructions for creating this design.
The user is assumed to have basic understanding of using ACE GUI. The user may refer to the online demo as well as the ACE documentation for different aspects of using the ACE GUI. Single-Lane Serdes Wrapper To generate a SerDes wrapper from ACE, the user needs to invoke ace following the instructions detailed in the ACE documentation. SerDes wrapper is created from the IP Configuration perspective.
To generate a SerDes wrapper, the user will need to double click on the link 12G SerDes in IP Libraries window. This will bring up the window for creating new IP (SerDes) configuration as shown in Figure 22: New IP Configuration Window. Tip: The windows listed above can be resized and moved around like any other GUI based applications. The windows can also be docked into ACE-GUI or undocked from ACE GUI.
Figure 23: New IP Configuration Window- Overview Page The user will now have the Overview page in the main window with the options for entering design parameters. The Outline and IP Diagram windows are also populated at this point, as shown in “Figure 24: Outline Window” and “Figure 25: IP Diagran Window”.
Overview Section: Initially, the main window in the middle will contain the Overview page as shown in Figure 26: New IP Configuration Window – Populating Overview Page. Figure 26: New IP Configuration Window – Populating Overview Page The entry fields and the available options are listed in Table 12: Entry fields for Overview page. This table also presents the choices that are made in Overview page (based on design properties listed in “Table 12: Entry fields for Overview page”).
Entry field Purpose Available Options Choice made Number of Lanes Number of lanes used by the design 1 to 12. 1 TX Data Rate (Gbps) TX data rate for the design 12 options ranging from 1.0265 to 11.31*1 10.3125 RX Data Rate (Gbps) RX data rate for the design is currently disabled. ACE GUI makes it equal to the TX Data Rate. *1 *3 18 options ranging from 60MHz to 350 MHz, including the reference frequency for typical protocols. *1 156.25 MHz Ref. Clock (MHz) Reference clock for SerDes PLL’s.
Entry field SerDes Lanes Purpose Available Options Choice made The specific lane used. Achronix FPGA has 64 SerDes lanes, 32 each on North and South sides. When North/South selected from Chip Edge combobox, option is given for each of the 32 lanes on corresponding side. *2 8 *1 The users may not use any combination of (a) TX (RX) data rate and (b) reference clock frequency.
Figure 27: Issues with Setting TX/RX data rate and reference clock frequency 56 UG028, July 1, 2014
Figure 28: Unavailable Fields As “Figure 28: Unavailable Fields” shows Some fields become unavailable based on earlier choices made by the user. In this case, the user chooses ‘XAUI’ as the standard (not related to simple_serdes_design) Note: For the data-rate above 5.0 GBPS (including 10.3125 GBPS), the ACE GUI eventually uses the wide-bus architecture and generates a wrapper that transmit/receive 40-bit data from/to fabric. A later section of this chapter further details the wide-bus architecture.
Figure 29: PMA Settings Window – First page The first page of the PMA Settings section gives the options to enter lane-specific PMA settings. This is not relevant to the current design since it uses a single SerDes lane. However, for completion, “Figure 30: Outline Window, When Lane-Specific PMA Settings are Enabled” shows the Outline sub-window when the user enables lane-specific RX PMA Equalization and lane-specific RX PMA PLL.
Figure 30: Outline Window, When Lane-Specific PMA Settings are Enabled RX PMA Equalization This page allows the user to change the PMA equalization settings on the receive path. The entry fields and the available options are listed in “Table 13: RX PMA Equalization”. This table also presents the choices that are made for the current design: simple_serdes_design. Note: All analog settings in “Table 13: RX PMA Equalization” and the tables to follow are provided for reference only.
Entry field Purpose High Freq AGC AC Boost Control AC boost of High frequency AGC DFE Pulseshaping Tap 3dB Freq 3dB Frequency of Pulse-Shaped Analog Decision Feedback Equalizer used to deal with channel loss DFE Pulseshaping Tap Gain Tap gain of Pulse-Shaped Analog Decision Feedback Equalizer used to deal with channel loss DFE N-1 Tap Gain Control (mV) DFE N-2 Tap Gain Control (mV) DFE N-3 Tap Gain Control (mV) DFE N-4 Tap Gain Control (mV) RX User Control From Fabric Available Options* 32 options
Table 14: RX PMA PLL Settings UG028, July 1, 2014 Entry field Purpose Available Options Choice made RX PPM Controls the frequency accuracy threshold (ppm) for lock detection in the CDR Text-box entry. The user may enter any value.
TX PMA Driver This page allows the user to configure the transmit driver settings on PMA.. The entry fields and the available options are listed in “Table 15: TX PMA Driver Settings”. This table also presents the choices that are made for the current design: simple_serdes_design.
Table 16: TX PMA PLL Settings Entry field Purpose Available Options Choice made TX PPM Configure the PPM difference between reference clock and divided down PLL clock to assert PLL lock status signal Text-box entry. The user may enter any value. 1000 (Default) Section on PCS Settings: The user can reach the PCS Settings section by browsing through the pages related to the PMA Settings section. Alternatively, the user may reach this section by clicking the PCS Settings link on the Overview window.
Figure 32: PCS Settings for Receiver – Default Settings RX PCS Settings This page allows the user to configure the RX PCS settings. The entry fields and the available options are listed in “Table 17: RX PCS Settings”. This table also presents the choices that are made for the current design: simple_serdes_design.
Entry field Purpose Available Options Choice made Elastic FIFO*3 Use Elastic FIFO*3 8B Mode*3 SKIP Mode*3 SKIP Word 0*3 Eanble ALT 0*3 ALT SKIP Word 0*3 Whether clock compensation block on PCS (i.e., EFIFO) will be used. Whether 8B mode will be used Skip mode used for EFIFO Skip Word used for EFIFO Whether Alternate word will be used Alternate SKIP Word used for EFIFO SKIP Word 1*3 Eanble ALT 1*3 ALT SKIP Word 1*3 SKIP Word 2*3 Similar to the parameters related to Skip Word 0.
RX PCS Symbol Alignment “Figure 33: PCS Settings for Receiver – Symbol Alignment” presents the RX PCS Symbol Alignment window with the choices pertaining to the current design: simple_serdes_design. Figure 33: PCS Settings for Receiver – Symbol Alignment The entry fields and the available options are listed in “Table 18: Symbol Alignment Settings (PCS)”. This table also presents the choices that are made for the current design: simple_serdes_design.
Entry field Purpose Word 0 Value of Word# 0, when enabled. Mask 0 Value of mask for word0 Enable Word 0 or Inverse of Word 0 Enable Seq 0 Whether word 0 or the inverse of it will be used Whether Seq0 will be used.
Entry field Purpose Alt Seq 1 Unlock Mode Unlock Count Lock Count Unlock Decrement Count When the unlock will be reported The number of unlocks before misalignment reported The number of locks before alignment is reported Decrement count for unlock Available Options Text field to enter userdefined value (available when Alt Seq 0 is enabled) • Misaligned • Decode Error • Decode or Disparity Choice made N/A since Alt Seq 0 is not enabled Misaligned Text field to enter userdefined value 3 Text fiel
Table 19: TX PCS Settings Entry field Purpose Available Options Disabled 8b/ 10b 128/130b 8B10B • • PBR0 PBR1 PBR0 • • • • True False True False • • True False • • • Encoder Choice made PBR Functions PBR Block Transmit Symbol Swap Transmit Bit Order Reverse User-Controlled Disparity and Error Forcing Whether PBR block is used. PBR0 is used on data before encoder (or when encoder is disabled). PBR1 is used on encoded data to PMA. Setting for PBR block on TX path.
Generation of Wrapper Files: The user can now generate wrapper files (src/ace folder) by clicking the Generate button. Note: The user can generate the wrapper files without going through all the pages. In other words, the user can use Generate button from any page to generate the wrapper files. If the user does not set values for one or more multiple pages, ACE will use the default values for the corresponding configurations.
If the files are successfully generated, the user will find the corresponding message on the TCL sub-window, as shown in “ Figure 36: TCL console message upon successful generation of wrapper files”.
Integration of SerDes Wrapper in a Design This section details how to use the files generated by ACE GUI into a user-design. For readyreference, the design properties from “Design Flow: Creating a SerDes Design” are presented again: Design name : simple_serdes_design Objective : Send data from fabric to SerDes and read-back data using internal loopback. Data rate : 10.3125 Gbps Standard : Generic Number of lanes : 1 Placement : South lane# 8 Ref. clock : 156.
iSerDes is chosen as the Hierarchical Instance Path, the generated .sdc and .pdc files need not be modified. “Table 20: Signals passed between the SerDes Instance and the Top-Level module” gives a list of the ports in the SerDes wrapper that are accessed from the top-level module of the current design. The corresponding signal names used in the top-level module are also listed in this Table.
SerDes Port Name Top-level Signal-name Comments whether the SerDes is ready. For instance, ln0_TX_ready indicates that the SerDes is ready for data receipt. These signals can be used for debugging and other purposes. For instance, ln0_TX_ready can be used to start data transmission.
Dynamically Changing the SerDes Register Values Typically the PMA/PCS registers need not be changed during runtime. However, simple_serdes_design uses internal SerDes loopback. Internal loopback may be the starting point for the users to verify the functionality of any user-design. To enable the internal loopback, the user needs to dynamically ( at run-time) set a PCS register via the SBUS interface.
.i_reg_wr_data (unused_ln0_i_reg_wr_data), // data for write .o_reg_rd_data (unused_ln0_o_reg_rd_data), // data from read (latch when o_reg_rdwr_valid) .o_reg_rdwr_valid (unused_ln0_o_reg_rdwr_valid) // action finished (high for one cycle) ); Note: Not all registers can be modified dynamically. For a list of the dynamic registers, please contact Achronix Customer Support.
Note: When 10’h1BC is transmitted from the fabric, the output of the 8b/10b decoder on the PCS receiver path will be 10’h283 (alternate: 10’h17C).
the placement of SerDes-Reset signal (ln0_rst_hard); TX-ready status signal (ln0_TX_ready) and the placement of the sbus-clock that is required to set internal-loopback through sbus interface # Manually entered Design-specific: For providing sbus-clock for sbus-interface # The pin (pad0_clk_bank_se) refers to the clock-supply used in Achronix Validation Board.
create_generated_clock iSERDES.x_ch0.iffdmux.GEN_CLKDIV.TX.iTXclkdiv/clk_out –source iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_TX_data_clk -divide_by 2 create_generated_clock iSERDES.x_ch0.iffdmux.GEN_CLKDIV.RX.RX.iRXclkdiv/clk_out source iSERDES.x_ch0.u_serdes_wrap.
Design Guidelines This section will first present the coding practice that the user is recommended to use. Reset Sequence The following sequence is presented as a guidance to define the reset sequence to be used with a typical SerDes application. 1. Deassert hard-reset (ch0_i_rst_hard_n in “Table 20: Signals passed between the SerDes Instance and the Top-Level module”) 2. Wait for 1200us; registers within SerDes can be programmed during this time.
UG028, July 1, 2014 • All clocks from SerDes lanes 0 to 14 on the South Side of the Chip enter the far SouthWest clock region. • All clocks from SerDes lanes 20 to 31 on the South Side of the Chip enter the far SouthEast clock region. • All clocks from SerDes lanes 15 to 19 on the South Side of the Chip enter BOTH the far SouthWest and far SouthEast clock regions. Avoid using these lanes if possible.
Figure 37: Clock Region View 82 UG028, July 1, 2014
The following factors determine how many clocks enter the Core for each SerDes lane or bonded group of lanes: • Use of Hard IP Controllers: If you are using a hard IP controller, such as Interlaken, Ethernet, or PCIe, then the number of clock resources entering the Core is determined by the number of clocks on the hard IP controller. All raw SerDes clocks connect to the hard IP controllers and do not enter the Core.
• SerDes lanes on the chip are divided into physical groups of 8 lanes (0-7), 12 lanes (819) and 12 lanes (20-31) on the North and South sides of the chip, as seen in Figure 38 – Physical assignment of SerDes Lanes below. Figure 38: Physical assignment of SerDes Lanes 84 • Channel bonding of multiple lanes is limited to fit within the boundaries of each group.
Figure 39: SerDes Placement Guidelines • Avoid lanes 15-19 (on North and South) when not using channel bonding, since these lanes consume clock resources in both East and West clock regions. This is not a hard rule, but is something to be aware of when calculating clock resources. Example of managing clock resources: Let’s say we want to use all 32 SerDes lanes on the North side of the chip. We will not be using the hard IP controllers.
lanes. Now we have a total of 4 clocks per bonded group of 12 lanes, or 8 total clocks for the 24 10 Gbps lanes. At this point, we have a total of 16 clock resources needed for the SerDes (8 for the 5 Gbps lanes and 8 for the 10 Gbps lanes). Now we need to place the SerDes lanes. Since the chip allows bonded groups of lanes to be placed on lanes 0-7, 8-19, and 20-31, we can easily see that our groups of 12 bonded lanes will not fit on lanes 0-7.
Design Tips Timing report of a routed design: When a design passes through the place-and-route tool, please make sure that there is no setup- and/or hold-time violation for the routed design. Section-4 of the ACE User Document provides a detailed description of checking the timing reports generated by ACE. Bringing up debug/status signals from the top-level RTL: To facilitate debugging of a design, we can bring up the SerDes status signals to on-board LED’s and/or SMA/SMP connectors.
For our sample design, we have defined data-rate=10.3125gbps and data-width=20. For this higher-rate, the wide-bus architecture will be used. In other words, 40-bits data will be transmitted to and received from SerDes. The frequency for both TX and RX clock will then be 257.81 MHz: Equation 2 10.3125 𝐷𝑎𝑡𝑎 _𝑟𝑎𝑡𝑒 = 257.81 𝑀𝐻 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 = 𝑑𝑎𝑡𝑎 _𝑡𝑟𝑎𝑛𝑠𝑚𝑖𝑠𝑠𝑖𝑜𝑛_𝑤𝑖𝑑𝑡ℎ = 40 We should have clocks toggling at ~129 MHz for both ln0_TXclk_div2 and ln0_RXclk_div2.
Overview of the modification: With respect to the steps followed in creating simple_serdes_design, the following modifications are made in preparing simple_serdes_design_efifo: 1. Changes in using ACE GUI during wrapper generation. 2. Changes in RTL code related to using clock signals generated by SerDes. 3. Changes in ace_placement.pdc and ace_constraint.sdc related to using clock signals from SerDes. These modifications are detailed below.
Entry field Eanble ALT 0*3 ALT SKIP Word 0*3 SKIP Word 1*3 Eanble ALT 1*3 ALT SKIP Word 1*3 SKIP Word 2*3 Eanble ALT 2*3 ALT SKIP Word 2*3 Transition Density Checker (TDC) Enable Transition Density Checker*3 Max Count*3 Max Count Scaling Factor*3 Available Options • True • False Text field to select user-defined value (available only when Enable ALT 1 is selected Text field to select user-defined value • True • False Text field to select user-defined value (available only when Enable ALT 0 is selected Tex
Figure 40: PCS Settings for Receiver – Configurations for Decoder and Elastic FIFO Now, just as we did for the design without clock-compensation (simple_serdes_design), we can generate the design files from the ACE GUI for our design with clock compensation (simple_serdes_design_efifo). Modification – 2 (RTL Code): The comma character that has previously been used for symbol alignment is used as EFIFO SKIP word in this derivative of the design.
Related modifications are listed below: Simple_serdes_design_efifo_wrapper iSerDes ( // ============================= // Lane 0 // ********************** // Inputs to SerDes // ********************** .. .. .. .. .. .. // ********************** // Outputs from SerDes // ********************** // Data received from SerDes .. .. .. .. .. .. // Clocks from SerDes .ch0_o_TX_data_clk (ln0_TX_clk), .ch0_o_RX_data_clk (ln0_RX_clk_unused), // okay to keep floating as well.
Modification – 3 (placement and timing constraints): Since there is only one divide-by-two clock in this derivative of the design, we can remove the placement for ln0_RXclk_div2 from ace_placement.pdc. Contents of the ace_constraints.sdc file can be copied from the ACE generated .sdc file except for the constraints related to the user-defined clocks (such as, reference clocks and snapshot clocks). Design Bypassing PCS: There are two modes for bypassing a PCS: 1.
Note: Although the PCS modules are disabled, the SerDes will still generate two clocks for transmit and receive ends (from PMA). Unlike the design with EFIFO enabled (simple_serdes_design_efifo), these two clocks are not aligned. The changes for this derivative of the design are presented below. Modification – 1 (ACE GUI): Mode – a (Bypassing PCS Modules without Disabling PCS): While generating GUI wrapper for this derivative, we need to disable the followings: 1.
Note: When compared with the sample design (simple_serdes_design), no change is required in ace_placement.pdc or in ace_constraint.sdc files for this derivative (simple_serdes_design_pcs_bypassed). The instantiation of the SerDes wrapper will remain same. Figure 41: Disabling PCS from ACE GUI Bypassing PCS by Manually Overriding Corresponding Register This section presents use an alternative approach for bypassing PCS through the Advanced section in ACE GUI.
Figure 42: Modifying Register Settings from ACE GUI To bypass the PCS block, the bit-4 of Reg[17A] needs to be set to 1’b1, i.e., 17A needs to be set at 8’h10. To do that, the user needs to follow the steps listed below: 96 • Type 17A in start address and hit tab on keyboard to have the address 17A. • Select 17A on the table in the middle so that ‘17A’ is displayed in the text-field titled AHB address.
Figure 43: Changing Value of Register 17A to bypass PCS block Note: Setting Reg[17A] at 8’h10 will automatically disable all PCS modules even if they are not disabled individually in ACE GUI.
Dynamic Read/Write of SerDes Registers via SBUS This chapter broadly categorizes the PMA and PCS registers into: 1. Static registers 2. Dynamic registers While the static registers are hardcoded into ACE generated GUI, the dynamic registers can be modified runtime. This chapter details the macros that can be used to modify the dynamic PCS/PMA registers. Typically, SerDes registers are programmed during FPGA configuration, and there is no need to program them dynamically.
ACX_SERDES_SBUS_IF Module The connection diagram for ACX_SERDES_SBUS_IF is shown in “Figure 44 Disabling PCS Decoder (default ACE Setting)”.
The Ports of ACX_SERDES_SBUS_IF Module: The signals (ports) shown in “Figure 43 Changing Value of Register 17A to bypass PCS block” and “The Ports of ACX_SERDES_SBUS_IF Module:” are detailed now. General signals: Port sbus_clk: There should be one ACX_SERDES_SBUS_IF instance per SerDes lane. For each lane, a clock signal is required to drive both the SerDes (input ports ch0_i_sbus_clk etc.) and ACX_SERDES_SBUS_IF (input port sbus_clk). The sbus_clk may be shared with multiple Serdes lanes.
Example of SerDes Register Access through SBUS: Setting Loopback Mode The SerDes must be in the “ready” state before it enters loopback mode. Therefore, the loopback mode cannot be configured with the bitstream, and must instead be configured in user mode. The ACE library provides the macro ACX_SERDES_LOOPBACK_CTRL to make that straightforward. To use this macro, use the following in your code: `include "speedster22i/macros/ACX_SERDES_LOOPBACK_CTRL.
SerDes signals Sbus_clk and ready signals: The sbus_clk and ready signals must be connected between SerDes lane and ACX_SERDES_LOOPBACK_CTRL. The sbus_clk must be connected to both SerDes lane and ACX_SERDES_LOOPBACK_CTRL. The sbus_clk may be shared with multiple SerDes lanes. The sbus_clk is normally generated by a PLL, and, for practical reasons, should be 50MHz or less. You cannot use the RX or TX clock for this.
); .i_pma_RXready(pma_RXready), // Use the IP Configuration Perspective in Ace to generate a Serdes wrapper gui_generated_serdes_wrapper iSERDES ( .ch0_i_sbus_clk (sbus_clk), .ch0_i_sbus_data (to_sbus_data), .ch0_i_sbus_req (to_sbus_req), .ch0_i_sbus_sw_rst (to_sbus_sw_rst), .ch0_o_sbus_ack (from_sbus_ack), .ch0_o_sbus_data (from_sbus_data), .ch0_o_pma_RXready (pma_RXready), .ch0_o_pma_TXready (pma_TXready), .ch0_o_pma_synthready (pma_synthready) ....
Electrical Specifications Operating Conditions Table 22: Operating Conditions Parameter Notes Min Typical Max Unit 0.90 0.95 1.05 V 1.71 1.80 1.98 V 0.90 0.95 1.05 V 1.71 1.80 1.98 V 0.03 Vpkpk 0.03 Vpkpk 0.05 Vpkpk 0.05 Vpkpk 85 125 °C °C DC Power-Supply Pin Requirements VDD1DC-BUMP VDD2DC-BUMP VDD1DC-IC VDD2DC-IC 0.95V DC analog core supply voltage (specified at bump pins) 1.8V nominal DC analog IO voltage (specified at bump pins) 0.
Transmitter Table 23: DC and AC Switching Characteristics Parameter Description Min Typical Max Unit Output Eye Specification VTX-DIFF-PKPK Backporch Transmit Amplitude 400 1500 mVdiffpkpk mVdiff- VTX-EYE-PKPK Transmit Eye Voltage Opening 400 1200 DTX-N+1-DEEMP DTX-N-1-DEEMP DTX-N-2-DEEMP TTX-SLEW N+1 precursor Tap De-Emphasis N-1 postcursor Tap De-Emphasis N-2 postcursor Tap De-Emphasis Rise/Fall Time Transmit Dependant Jitter (InterSymbol Interference) at 8Gbps.
Parameter ZTX-DIFF-HIZ ZTX-CM-HIZ Description Min Typical Transmitter Output Differential DC Impedance in Squelch Mode Transmitter Output Common-Mode DC Impedance in Squelch Mode Max Unit >2k Ω >500 Ω -14 dB -6 dB -6 dB -4 dB 20 mVpkpk 50 mV 8 ns 600 mV Transmitter Return Loss ZRL-DIFF-DC ZRL-DIFF-NYQ ZRL-CM-DC ZRL-CM-NYQ Transmitter Differential DC Return Loss Transmitter Differential Return Loss at Nyquist Frequency (FBAUD/2) Transmitter Common-Mode DC Return Loss Transmitter C
Table 25: Return Loss Standard Differential DC return loss Differential return loss at FBAUD/2 Common mode DC return loss Common mode return loss at FBAUD/2 PCIe Gen1 10 10 6 6 dB Yes PCIe Gen2 10 8 6 6 dB Yes dB Yes PCIe Gen3 UG028, July 1, 2014 Units Compliant? XAUI 10 5.9 -- -- dB Yes CEI 6G – SR/LR 8 8 6 6 dB Yes FC-1 12 12 12 11.1 dB Yes FC-2 12 9.5 12 7.
Receiver Table 26: DC and AC Switching Characteristics Parameter VRX-DIFF-PKPK Min VRX-CM-DC Differential Input Peak to Peak Voltage for AC coupnling Receiver Input DC Common Mode Voltage VRX-CM-AC Receiver Input AC Common Mode Voltage -150 VRX-SENS Receiver Input Voltage Sensitivity 30 FPPM-OFFSET Frequency tolerance 5350 VRX Common mode AC return loss (standard specific) Power down DC input impedance Input common mode frequency Total Jitter Tolerance Random Jitter Tolerance Deterministic Jit
Parameter Description ZRL-CM-NYQ Receiver Common-Mode Return Loss at Nyquist Frequency (FBAUD/2) Min Typ Max Unit -4 dB 110 27.
Parameter Description Min Typ 40 50 Max Unit Receiver Input Voltage Sensitivity Under the Following Conditions: 50inch of FR4 • VRX-SENS • • TRX-TJ NGPLL pkpk 6.25Gbps PRBS7 data pattern Receive Input Signal Data Dependant Jitter (Inter-Symbol Interference). Receive Input Signal Total Jitter (Inter-Symbol Interference). F3dB cutoff frequency for the 1st Order HighPass Jitter Measurement Filter.
Standard X1 (UI) X2 (UI) 2xVp-min (mV) 2xVp-max (mV) OIF CEI 6G – LR FC-1 FC-2 FC-4 SATA Gen1 SATA Gen2 SAS Rev5 0.475 0.33 0.35 0.33 0.325 0.325 0.325 0.5 0.5 0.5 0.5 0.5 0.5 0.
Reference Clock The electrical specifications for the reference clock are summarized in the following tables Table 29: Reference Clock Electrical Speficiations Parameter FREF TREF TREF-DUTY TREF-RISE/FALL TREF-SINGLEENDSKEW TREF-PPM-ERROR ZREF-SINGLEEND-DC ZREF-DIFF-DC VREF-DIFF VREF-CM TREF-RMS-MAX Description Reference clock operating frequency range Reference clock operating frequency range Duty Cycle Rise and falling edge rate Min Max Unit 50 250 MHz 4 20 ns 60 0.
Revision History The following table shows the revision history for ths document. UG028, July 1, 2014 Date Version 3/29/2013 4/22/2013 5/21/2013 4/30/2014 6/3/14 7/1/14 1.0 1.1 1.2 1.3 2.0 2.1 Revisions First customer release Updated ref clk frequencies Corrected some formatting issues Complete overhaul of the document Reformatted.
