Speedster22i Macro Cell Library UG021 v1.7 – Oct 24, 2014 www.achronix.
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Table of Contents Preface ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ xiv Introduction ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ xiv Cell Naming Conventions ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ xv Register Naming Conventions ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ xv I
Registered Differential Input Pad with Asynchronous or Synchronous Set/Reset ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 22 Verilog Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 23 VHDL Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 23 IPAD_DIFFD2 ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 24 DDR Different
Pins ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 48 Parameters ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 48 init ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 48 Verilog Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
DFFN ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 62 Negative Clock Edge D‐Type Register‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 62 Pins ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 62 Parameters ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
init ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 74 Verilog Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 75 VHDL Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 75 DFFNS ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
Two Input Adder / Subtractor with Programmable Load ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 86 Pins ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 86 Parameters ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 87 invert_b ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
en_out_reg ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ reg_initval ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ reg_srval ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ reg_rstval ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
BRAM80KECC ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 147 80k‐bit Simple Dual‐Port Memory with Error Correction ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 147 BRAM80KECC Pins ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 148 Parameters ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 148 en_out_reg ‐
rst_sync_mode ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ wrrst_sync_stages ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ rdrst_sync_stages ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ afull_offset ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
regce_priority_sub ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ regce_priority_cin ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ regce_priority_dout ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ reg_a ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
PLL Control ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 196 Serial Control Bus (SCB) ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 196 Control Status Registers (CSR) Register Description ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ 197 Verilog Instantiation Template ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐
PAGE xiii www.achronix.
Preface Introduction The Achronix Macro Cell Library provides the user with building blocks that may be instantiated into the user’s design. These macros provide access to low‐level fabric primitives, complex I/O block, and higher level design components. Each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.
Cell Naming Conventions Cell Naming Conventions Register Naming Conventions DFFNER Reset Blank – No reset input R – Reset (has priority over enable) S – Set (has priority over enable) C – Clear (enable has priority) P – Preset (enable has priority) Enable blank – No enable input E – Enable input Clock Edge Blank – Positive‐edge register N – Negative‐edge register Cell Type DFF – D‐type register I/O Cell Naming Conventions IOPAD_DIFFD_DL Delay Mode Blank ‐ No Delay Line DL ‐ Programmable Delay Line Registe
Conventions Used in this Guide Conventions Used in this Guide Item Format Examples Command-line entries Formatted with the Courier bold font face. $ Open top_level_name.log File Names Formatted with the Courier font face. filename.ext GUI buttons, menus and radio buttons Formatted with the Helvetica bold font face. Click OK to continue. File Open Variables Formatted with italic emphasis. design_dir/output.
Chapter 1 – I/O Cells Table 1-1: Supported Single-Ended Voltage Standards I/O Standard Parameter Output Input VREF VDDO VDDI (1) (Volts) (Volts) (Volts) Description HSTL15_I 1.5 1.5 0.75 1.5V HSTL, type I HSTL15_II 1.5 1.5 0.75 1.5V HSTL, type II HSTL18_I 1.8 1.8 0.90 1.8V HSTL, type I HSTL18_II 1.8 1.8 0.90 1.8V HSTL, type II LVCMOS12 1.2 1.2 0.60 1.2V LVCMOS LVCMOS15 1.5 1.5 0.75 1.5V LVCMOS LVCMOS18 1.8 1.8 0.90 1.8V LVCMOS SSTL15_I 1.5 1.5 0.75 1.
I/O Cells IOPAD IOPAD Bidirectional I/O Pad IOPAD oe din pad dout Figure 1-1: IOPAD Logic Symbol IOPAD is an asynchronous I/O pad with active‐high clock enable. Table 1-3: Ports Name Type Description pad inout Bidirectional device pad. din input Data input. dout output Data output. The dout pin is driven with the value present on the pad pin.
I/O Cells IOPAD Verilog Instantiation Template IOPAD #(.location(""), .iostandard("LVCMOS18"), .drive("16"), .slew("slow"), .keepmode("none"), .open_drain("false"), .hysteresis("none"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.din(user_din), .dout(user_dout), .oe(user_oe), .pad(user_pad)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells IOPAD_D IOPAD_D Bidirectional Registered I/O Pad with Asynchronous or Synchronous Set/Reset oerstn oe oeclk IOPAD_D rstn d q ce txrstn din txdata_en txclk rstn d q ce srstn pad rstn d q ce srstn dout rxrstn rxdata_en rxclk srstn Note: For Speedster22iHP, txdata_en and rxdata_en are shared. For Speedster22iHD, txdata_en and rxdata_en may be driven separately.
I/O Cells IOPAD_D Table 1-7: Ports Name pad Type Description inout Bidirectional device pad. input Positive-edge based data input. If parameter txregmode=”reg”, data is clocked into the din register upon the rising edge of the clk input, and is driven to the pad if the oe input was high before the rising edge of the clk input. If parameter txregmode=”nonreg”, din is driven to the pad when the output is enabled (oe=1). output Positive-edge based data output.
I/O Cells IOPAD_D Table 1-8: Parameters Parameter Defined Values Default Value “” ““ See Table 1‐1 “LVCMOS18” "2", "4", "6", "8", "12", "16" "16" txregmode “reg”, ”nonreg” “reg” rxregmode “reg”, ”nonreg” “reg” oeregmode “reg”, ”nonreg” “reg” rstmode “sync”, “async” “async” location iostandard drive rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” keepmode "pullup", "pulldown", "none" “none” hysteresis "none", "schmitt" “none” open_drain “true”, “fal
I/O Cells IOPAD_D Verilog Instantiation Template IOPAD_D #(.location(""), .iostandard("LVCMOS18"), .drive("16"), .txregmode("reg"), .rxregmode("reg"), .oeregmode("reg"), .rstmode("async"), .rstvalue("low"), .slew("slow"), .keepmode("none"), .hysteresis("none"), .open_drain("false"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.pad(user_pad), .din(user_din), .dout(user_dout), .oe(user_oe), .txdata_en(user_txdata_en), .rxdata_en(user_rxdata_en), .txrstn(user_txrstn), .
I/O Cells IOPAD_D -- Component Instantiation IOPAD_D_instance_name : IOPAD_D generic map (location => ““, iostandard => “LVCMOS18”, drive => "16", txregmode => “reg”, rxregmode => “reg”, oeregmode => “reg”, rstmode => “async”, rstvalue => “low”, slew => “slow”, keepmode => "none", hysteresis => "none", open_drain => "false", pvt_comp => "none, termination => "50", odt => "off") port map (pad => user_pad, din => user_din, dout => user_dout, oe => user_oe, txrstn => user_txrstn, srstn => user_srstn, rxrstn
I/O Cells IOPAD_D2 IOPAD_D2 Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/ Reset IOPAD_D2 oerstn oe rstn d q ce d rstn d q ce d rstn rstn q q txclk txrstn dina rstn d q ce srstn d rstn q pad dinb txdata_en rstn d q ce srstn d rstn q txclk rxdata_en rxrstn d d rstn rstn q q rstn d q ce srstn rstn d q ce srstn douta doutb srstn rxclk Note: For Speedster22iHP, txdata_en and rxdata_en are shared.
I/O Cells IOPAD_D2 Table 1-12: Ports Name pad dina dinb Type Description inout Bidirectional device pad. input Positive-edge based data input. Data is clocked into the dina register upon the rising edge of the txclk input when the txdata_en signal is high. It is routed to the pad on the following rising edge of the clock.
I/O Cells IOPAD_D2 Table 1-12: Ports (Continued) Name Type oeclk input Description Output Enable Register Clock Input.
I/O Cells IOPAD_D2 Verilog Instantiation Template IOPAD_D2 #(.location(""), .iostandard("LVCMOS18"), .drive("16"), .rstmode("async"), .rstvalue("low"), .slew("slow"), .keepmode("none"), .hysteresis("none"), .open_drain("false"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.pad(user_pad), .dina(user_dina), .dinb(user_dinb), .douta(user_douta), .doutb(user_doutb), .oe(user_oe), .txdata_en(user_txdata_en), .rxdata_en(user_rxdata_en), .txrstn(user_txrstn), .rxrstn(user_rxrstn), .
I/O Cells IPAD IPAD Non-Registered Input Pad IPAD pad dout Figure 1-6: IPAD Logic Symbol IPAD is an asynchronous input pad. Table 1-14: Ports Name Type Description pad input Device pad. dout output Data output.
I/O Cells IPAD VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation IPAD_instance_name : IPAD generic map (location => ““, iostandard => “LVCMOS18”, keepmode => “none”, hysteresis => "none", pvt_comp => "none", termination => "50", odt => "off") port map (dout => user_dout, pad => user_pad); Speedster Macro Cell Library www.achronix.
I/O Cells IPAD_D IPAD_D Registered Input Pad with Asynchronous or Synchronous Set/Reset IPAD_D rstn pad rstn d q ce data_en clk dout Figure 1-7: IPAD_D Logic Symbol IPAD_D is a registered input pad. Driving rstn low performs either a synchronous or asynchronous reset of the input register as determined by the value of the rstmode parameter. Upon assertion of the rstn signal, the input register is initialized to the value determined by the rstvalue parameter.
I/O Cells IPAD_D Table 1-19: Input Function table pad rxdata_en rxclk dout 0 1 0 1 1 1 X 1 X Z 1 X X,Z 0 Hold previous data Verilog Instantiation Template IPAD_D #( .location(""), .iostandard("LVCMOS18"), .rstmode("async"), .rstvalue("low"), .keepmode("none"), .hysteresis("none"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.pad(user_pad), .dout(user_dout), .rstn(user_rstn), .data_en(user_data_en), .
I/O Cells IPAD_D2 IPAD_D2 DDR Input Pad with Asynchronous or Synchronous Set/Reset IPAD_D2 data_en rstn pad d d rstn rstn q rstn d q ce douta q rstn d q ce doutb clk Figure 1-8: IPAD_D2 Logic Symbol IPAD_D2 is a Double Data Rate (DDR) input pad. There is an additional register stage on the input to allow the logic level on the pad to changes on both the rising and falling edges of the clock, but allow the interface signals to and from the FPGA core to change on the rising edge of the clock.
I/O Cells IPAD_D2 Table 1-21: Parameters Parameter Defined Values Default Value “” ““ See Table 1‐1 “LVCMOS18” "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” keepmode "pullup", "pulldown", "none" “none” hysteresis location iostandard drive "none", "schmitt" “none” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” “off”, “on” “off” “50”, “60”, “75”, “100”, “120”, “240”
I/O Cells IPAD_D2 keepmode => "none", hysteresis => "none", pvt_comp => "none, termination => "50", odt => "off") port map (pad => user_pad, douta => user_douta, doutb => user_doutb, oe => user_oe, rstn => user_rstn, clk => user_clk); Speedster Macro Cell Library www.achronix.
I/O Cells IPAD_DIFF IPAD_DIFF Non-Registered Differential Input Pad IPAD_DIFF pad padn dout Figure 1-10: IPAD_DIFF Logic Symbol IOPAD is a non‐registered differential input pad with complementary input pads pad and padn with output dout. Table 1-22: Ports Name Type Description pad input Device pad. padn input Complement Device pad. The padn input must be driven with the logical complement of the pad input. dout output Data output.
I/O Cells IPAD_DIFF Verilog Instantiation Template IPAD_DIFF #(.locationp(""), .locationn(""), .iostandard("LVDS"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.dout(user_dout), .pad(user_pad) .padn(user_padn)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells IPAD_DIFFD IPAD_DIFFD Registered Differential Input Pad with Asynchronous or Synchronous Set/Reset IPAD_DIFFD rstn pad padn data_en clk rstn d q ce dout Figure 1-11: IPAD_DIFFD Logic Symbol IPAD_DIFFD is a registered differential input pad. Driving rstn low performs either a synchronous or asynchronous reset of the input register as determined by the value of the rstmode parameter.
I/O Cells IPAD_DIFFD Table 1-27: Input Function table pad padn rxdata_en rxclk dout 0 1 1 0 1 0 1 1 X X 1 X Z Z 1 X X X 0 Hold previous data Z Z 0 Hold previous data Verilog Instantiation Template IPAD_DIFFD #( .locationp(""), .locationn(""), .iostandard("LVDS"), .rstmode("async"), .rstvalue("low"), .pvt_comp("none"), .termination("50"), .odt("off")) instance_name (.pad(user_pad), .padn(user_padn), .dout(user_dout), .rstn(user_rstn), .
I/O Cells IPAD_DIFFD2 IPAD_DIFFD2 DDR Differential Input Pad with Asynchronous or Synchronous Set/ Reset IPAD_DIFFD2 data_en rstn pad padn d d rstn rstn q rstn d q ce douta q rstn d q ce doutb clk Figure 1-12: IPAD_DIFFD2 Logic Symbol IPAD_D2 is a differential Double Data Rate (DDR) input pad.
I/O Cells IPAD_DIFFD2 Table 1-29: Parameters Parameter Defined Values Default Value locationp “” ““ locationn “” ““ iostandard See Table 1‐1 “LVCMOS18” drive "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” keepmode "pullup", "pulldown", "none" “none” hysteresis "none", "schmitt" “none” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” “off”, “on” “of
I/O Cells IPAD_DIFFD2 generic map (location => ““, iostandard => “LVCMOS18”, rstmode => “async”, rstvalue => “low”, keepmode => "none", hysteresis => "none", pvt_comp => "none, termination => "50", odt => "off") port map (pad => user_pad, padn => user_padn, douta => user_douta, doutb => user_doutb, oe => user_oe, rstn => user_rstn, clk => user_clk); Speedster Macro Cell Library www.achronix.
I/O Cells OPAD OPAD Non-Registered Output Pad OPAD din pad Figure 1-14: OPAD Logic Symbol OPAD is an non‐registered output pad. Table 1-30: Ports Name Type din input pad output Description Data input. Device output pad. The data at the din input is driven to the pad output.
I/O Cells OPAD VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation OPAD_instance_name : OPAD generic map (location => "", iostandard => "LVCMOS18", drive => "16", slew => "slow", pvt_comp => "none") port map (din => user_din, pad => user_pad); Speedster Macro Cell Library www.achronix.
I/O Cells OPAD_D OPAD_D Registered Output Pad with Asynchronous or Synchronous Set/Reset OPAD_D rstn din data_en clk rstn d q ce pad Figure 1-15: OPAD_D Logic Symbol OPAD_D is a registered output pad. The output register is clocked on the rising edge of the clock. Driving rstn low performs an asynchronous initialization of the output register if the rstmode parameter is set to async and performs a sychronous initialization of the output register if the rstmode parameter is set to sync.
I/O Cells OPAD_D Table 1-34: Parameters Parameter Defined Values Default Value “” ““ See Table 1‐1 “LVCMOS18” "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” location iostandard drive Table 1-35: Output Function Table (rstmode = “async”) din data_en rstn clk pad 0 1 1 0 1 1 1 1 Table 1-36: Output Function Ta
I/O Cells OPAD_D VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells OPAD_D2 OPAD_D2 DDR Output Pad with Asynchronous or Synchronous Set/Reset OPAD_D2 rstn rstn d q ce dina d rstn q pad rstn d q ce dinb data_en d rstn q clk Figure 1-16: OPAD_D2 Logic Symbol OPAD_D2 is a Double Data Rate (DDR) output pad with active‐high registered output enable.
I/O Cells OPAD_D2 Table 1-38: Parameters Parameter Defined Values Default Value “” ““ See Table 1‐1 “LVCMOS18” "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” keepmode "pullup", "pulldown", "none" “none” hysteresis location iostandard drive "none", "schmitt" “none” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” “off”, “on” “off” “50”, “60”, “75”, “100”, “120”, “240”
I/O Cells OPAD_D2 VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells OPAD_DIFF OPAD_DIFF Non-Registered Differential Output Pad OPAD_DIFF pad padn din Figure 1-18: OPAD_DIFF Logic Symbol OPAD_DIFF is an asynchronous differential output pad with input din and outputs pad and padn. Table 1-39: Ports Name Type Description din input pad output Data input. Device output pad. The data at the din input is driven to the pad output. padn output Device complement output pad. The logical inverse of the data at the din input is driven to the padn output.
I/O Cells OPAD_DIFF instance_name (.din(user_din), .pad(user_pad), .padn(user_padn)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells OPAD_DIFFD OPAD_DIFFD Registered Differential Output Pad with Asynchronous or Synchronous Set/Reset rstn oe clk din data_en OPAD_DIFFD rstn d q ce rstn d q ce pad padn Figure 1-19: OPAD_DIFFD Logic Symbol OPAD_DIFFD is a registered differential output pad. The output and output enable registers are clocked on the rising edge of the clock. The active‐high oe register is asynchronously cleared upon a low on the rstn input.
I/O Cells OPAD_DIFFD Table 1-43: Parameters Parameter Defined Values Default Value locationp “” ““ locationn “” ““ iostandard See Table 1‐2 “LVDS” drive "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” invert_out “off”, ”on” “off” Table 1-44: Output Function Table (rstmode = “async”) din data_en oe rstn
I/O Cells OPAD_DIFFD VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells OPAD_DIFFD2 OPAD_DIFFD2 DDR Differenctial Output Pad with Asynchronous or Synchronous Set/Reset OPAD_DIFFD2 rstn rstn d q ce dina d rstn q pad padn rstn d q ce dinb data_en d rstn q clk Figure 1-20: OPAD_DIFFD2 Logic Symbol OPAD_DIFFD2 is a Double Data Rate (DDR) differential output pad with active‐high registered output enable.
I/O Cells OPAD_DIFFD2 Table 1-47: Parameters Parameter Defined Values Default Value locationp “” ““ locationn “” ““ iostandard See Table 1‐1 “LVCMOS18” drive "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” keepmode "pullup", "pulldown", "none" “none” hysteresis "none", "schmitt" “none” invert_out “on”, “off” “off” open_drain “true”, “false” “false” pvt_comp “none”,
I/O Cells OPAD_DIFFD2 VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
I/O Cells TPAD TPAD Non-Registered Tristate Output Pad TPAD oe din pad Figure 1-22: TPAD Logic Symbol TPAD is an non‐registered tristate output pad. Table 1-48: Ports Name Type Description din input Data input. oe input Output Enbale. The data at the din input is driven to the pad output when the oe input is driven high. The pad output will be driven into highimpedance mode when oe is low. pad output Device output pad.
I/O Cells TPAD VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation TPAD_instance_name : TPAD generic map (location => "", iostandard => "LVCMOS18", drive => "16", slew => "slow", keepmode => “none”, open_drain => “false”, pvt_comp => "none") port map (din => user_din, oe => user_oe, pad => user_pad); Speedster Macro Cell Library www.achronix.
I/O Cells TPAD_D TPAD_D Registered Tristate Output Pad with Asynchronous or Synchronous Set/Reset rstn oe clk din data_en TPAD_D rstn d q ce rstn d q ce pad Figure 1-23: TPAD_D Logic Symbol TPAD_D is a registered output pad. The output and output enable registers are clocked on the rising edge of the clock. The active‐high oe register is asynchronously cleared upon a low on the rstn input.
I/O Cells TPAD_D Table 1-52: Parameters Parameter Defined Values Default Value “” ““ See Table 1‐1 “LVCMOS18” "2", "4", "6", "8", "12", "16" "16" rstmode “sync”, “async” “async” rstvalue “low”, “high” “low” slew “fast”, “slow” “slow” open_drain “true”, “false” “false” pvt_comp “none”, “own” “none” location iostandard drive Table 1-53: Output Function Table (rstmode = “async”) din data_en oe rstn clk pad X X X 0 X Z X 0 X 1 Hold previous data X
I/O Cells TPAD_D VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Chapter 2 – Registers Naming Convention These Macros are named based upon their characteristics and behavior. In each case, the name begins with DFF for D‐type Flip Flop. In addition to DFF each has one or more modifiers which indicates it’s unique properties.
Registers DFF Parameters Table 2-2: Parameters Parameter Defined Values init 1’b0, 1’b1 Default Value 1’b0 init The init parameter defines the initial value of the output of the DFF register. This is the value the register takes upon the initial application of power to the FPGA. The default value of the init parameter is 1’b0. Table 2-3: Function Table Inputs Output d ck q 0 0 1 1 Verilog Instantiation Template DFF #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .
Registers DFFE DFFE Positive Clock Edge D-Type Register with Clock Enable d ce ck DFFE q Figure 2-2: Logic Symbol DFFE is a single D‐type register with data input (d), clock enable (ce), and clock (ck) inputs and data (q) output. The data output is set to the value on the data input upon the next rising edge of the clock if the active‐high clock enable input is asserted. Pins Table 2-4: Pin Descriptions Name Type d input Description Data input. ce input Active-high clock enable input.
Registers DFFE Verilog Instantiation Template DFFE #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .ce(user_clock_enable), .ck(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFEC DFFEC Positive Clock Edge D-Type Register with Clock Enable and Synchronous Clear d ce ck cn DFFEC q Figure 2-3: Logic Symbol DFFEC is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐ low synchronous clear (cn) inputs and data (q) output. The active‐low synchronous clear input sets the data output low upon the next rising edge of the clock if it is asserted low and the clock enable signal is asserted high.
Registers DFFEC Table 2-9: Function Table Inputs Output cn ce d ck q X 0 X X Hold 0 1 X 0 1 1 0 0 1 1 1 1 Verilog Instantiation Template DFFEC #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .cn(user_clear), .ce(user_clock_enable), .ck(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFEP DFFEP Positive Clock Edge D-Type Register with Clock Enable and Synchronous Preset pn d ce ck DFFEP q Figure 2-4: Logic Symbol DFFEP is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐ low synchronous preset (pn) inputs and data (q) output. The active‐low synchronous preset input sets the data output high upon the next rising edge of the clock if it is asserted low and the clock enable signal is asserted high.
Registers DFFEP Table 2-12: Function Table Inputs Output pn ce d ck q X 0 X X Hold 0 1 X 1 1 1 0 0 1 1 1 1 Verilog Instantiation Template DFFEP #(.init(1’b1)) instance_name (.q(user_out), .d(user_din), .pn(user_preset), .ce(user_clock_enable), .ck(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFER DFFER Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset d ce ck rn q DFFER Figure 2-5: Logic Symbol DFFER is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐ low reset (rn) inputs and data (q) output. The active‐low reset input overrides all other inputs when it is asserted low and sets the data output low.
Registers DFFER sr_assertion The sr_assertion parameter defines the behavior of the output when the rn reset input is asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the reset signal, where the q output is set to zero upon assertion of the active‐low reset signal. Assigning the sr_assertion to “clocked” results in a synchronous assertion of the reset signal, where the q output is set to zero at the next rising edge of the clock.
Registers DFFER VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFES DFFES Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set sn d ce ck DFFES q Figure 2-6: Logic Symbol DFFES is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐ low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs when it is asserted low and sets the data output high.
Registers DFFES sr_assertion The sr_assertion parameter defines the behavior of the output when the sn set input is asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the reset signal, where the q output is set to one upon assertion of the active‐low reset signal. Assigning the sr_assertion to “clocked” results in a synchronous assertion of the reset signal, where the q output is set to one at the next rising edge of the clock.
Registers DFFES VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFN DFFN Negative Clock Edge D-Type Register d DFFN q ckn Figure 2-7: Logic Symbol DFFN is a single D‐type register with data input (d) and clock (ckn) inputs and data (q) output. The data output is set to the value on the data input upon the next falling edge of the clock. Pins Table 2-21: Pin Descriptions Name Type Description d input Data input. ckn input Negative-edge clock input. q output Data output.
Registers DFFN Verilog Instantiation Template DFFN #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .ckn(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFNEC DFFNEC Negative Clock Edge D-Type Register with Clock Enable and Synchronous Clear d ce ckn DFFNEC q cn Figure 2-8: Logic Symbol DFFNEC is a single D‐type register with data input (d), clock enable (ce), clock (ckn), and active‐low synchronous clear (cn) inputs and data (q) output. The active‐low synchronous clear input sets the data output low upon the next falling edge of the clock if it is asserted low and the clock enable signal is asserted high.
Registers DFFNEC Table 2-26: Function Table Inputs Output cn ce d ckn q X 0 X X Hold 0 1 X 0 1 1 0 1 1 1 0 1 Verilog Instantiation Template DFFNEC #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .cn(user_clear), .ce(user_clock_enable), .ckn(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFNEP DFFNEP Negative Clock Edge D-Type Register with Clock Enable and Synchronous Preset pn d ce ckn DFFNEP q Figure 2-9: Logic Symbol DFFNEP is a single D‐type register with data input (d), clock enable (ce), clock (ckn), and active‐low synchronous preset (pn) inputs and data (q) output. The active‐low synchronous preset input sets the data output high upon the next falling edge of the clock if it is asserted low and the clock enable signal is asserted high.
Registers DFFNEP Table 2-29: Function Table Inputs Output pn ce d ckn q X 0 X X Hold 0 1 X 1 1 1 0 1 1 1 0 1 Verilog Instantiation Template DFFNEP #(.init(1’b1)) instance_name (.q(user_out), .d(user_din), .pn(user_preset) .ce(user_clock_enable), .ckn(user_clock)); VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFNER DFFNER Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset d ce ckn rn DFFNER q Figure 2-10: Logic Symbol DFFNER is a single D‐type register with data input (d), clock enable (ce), clock (ckn), and active‐low reset (rn) inputs and data (q) output. The active‐low reset input overrides all other inputs when it is asserted low and sets the data output low.
Registers DFFNER sr_assertion The sr_assertion parameter defines the behavior of the output when the rn reset input is asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the reset signal, where the q output is set to zero upon assertion of the active‐low reset signal. Assigning the sr_assertion to “clocked” results in a synchronous assertion of the reset signal, where the q output is set to zero at the next falling edge of the clock.
Registers DFFNER VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFNES DFFNES Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set sn d ce ckn DFFNES q Figure 2-11: Logic Symbol DFFNES is a single D‐type register with data input (d), clock enable (ce), clock (ckn), and active‐low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs when it is asserted low and sets the data output high.
Registers DFFNES sr_assertion The sr_assertion parameter defines the behavior of the output when the sn set input is asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the set signal, where the q output is set to one upon assertion of the active‐low set signal. Assigning the sr_assertion to “clocked” results in a synchronous assertion of the set signal, where the q output is set to one at the next falling edge of the clock.
Registers DFFNES VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Registers DFFNR DFFNR Negative Clock Edge D-Type Register with Asynchronous Reset d q DFFNR ckn rn Figure 2-12: Logic Symbol DFFNR is a single D‐type register with data input (d), clock (ckn), and active‐low reset (rn) inputs and data (q) output. The active‐low reset input overrides all other inputs when it is asserted low and sets the data output low. If the asynchronous reset input is not asserted, the data output is set to the value on the data input upon the next falling edge of the clock.
Registers DFFNR Table 2-40: Function Table when sr_assertion = “unclocked’ Inputs Output rn d ckn q 0 X X 0 1 X X Hold 1 0 0 1 1 1 Table 2-41: Function Table when sr_assertion = “clocked’ Inputs Output rn d ckn q 0 X 0 1 X X Hold 1 0 0 1 1 1 Verilog Instantiation Template DFFNR #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .rn(user_reset), .
Registers DFFNS DFFNS Negative Clock Edge D-Type Register with Asynchronous Set sn d DFFNS q ckn Figure 2-13: Logic Symbol DFFNS is a single D‐type register with data input (d), clock (ckn), and active‐low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs when it is asserted low and sets the data output high. If the asynchronous set input is not asserted, the data output is set to the value on the data input upon the next falling edge of the clock.
Registers DFFNS Table 2-44: Function Table when sr_assertion = “unclocked’ Inputs Output sn d ckn q 0 X X 1 1 X X Hold 1 0 0 1 1 1 Table 2-45: unction Table when sr_assertion = “clocked’ Inputs Output sn d ckn q 0 X 1 1 X X Hold 1 0 0 1 1 1 Verilog Instantiation Template DFFNS #(.init(1’b1)) instance_name (.q(user_out), .d(user_din), .sn(user_set), .
Registers DFFR DFFR Positive Clock Edge D-Type Register with Asynchronous Reset d q DFFR ck rn Figure 2-14: Logic Symbol DFFR is a single D‐type register with data input (d), clock (ck), and active‐low reset (rn) inputs and data (q) output. The active‐low reset input overrides all other inputs when it is asserted low and sets the data output low. If the asynchronous reset input is not asserted, the data output is set to the value on the data input upon the next rising edge of the clock.
Registers DFFR Table 2-48: Function Table when sr_assertion = “unclocked’ Inputs Output rn d ck q 0 X X 0 1 X X Hold 1 0 0 1 1 1 Table 2-49: Function Table when sr_assertion = “clocked’ Inputs Output rn d ck q 0 X 0 1 X X Hold 1 0 0 1 1 1 Verilog Instantiation Template DFFR #(.init(1’b0)) instance_name (.q(user_out), .d(user_din), .rn(user_reset), .
Registers DFFS DFFS Positive Clock Edge D-Type Register with Asynchronous Set sn d DFFS q ck Figure 2-15: Logic Symbol DFFS is a single D‐type register with data input (d), clock (ck), and active‐low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs when it is asserted low and sets the data output high. If the asynchronous set input is not asserted, the data output is set to the value on the data input upon the next rising edge of the clock.
Registers DFFS Table 2-52: Function Table when sr_assertion = “unclocked’ Inputs Output sn d ck q 0 X 1 1 X X Hold 1 0 0 1 1 1 Table 2-53: Function Table when sr_assertion = “clocked’ Inputs Output sn d ck q 0 X X 1 1 X X Hold 1 0 0 1 1 1 Verilog Instantiation Template DFFS #(.init(1’b1)) instance_name (.q(user_out), .d(user_din), .sn(user_set), .
Chapter 3 – Logic Functions MUX2 Two Input Multiplexer Gate MUX2 din1 dout din0 sel Figure 3-1: Logic Symbol MUX2 implements a two‐input multiplexer gate that has each of the two data inputs (din0, din1) connected directly to the outputs of a pair of LUT4 blocks in an RLB. The MUX2, when combined with two LUT4s, can be used as either a LUT5, a 4:1 multiplexer, or a function of up to nine inputs. Pins Table 3-1: Pin Descriptions Name Type din0, din1 input Data inputs. input Data Selectinput.
Logic Functions MUX2 VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation MUX2_instance_name : MUX2 port map (dout => user_out, sel => user_sel, din0 => user_din0, din1 => user_din1); Speedster Macro Cell Library www.achronix.
Chapter 4 – Lookup Table (LUT) Functions LUT4 Four Input Lookup Table din0 din1 din2 din3 LUT4 q Figure 4-1: Logic Symbol LUT4 implements a four‐input lookup table with data inputs (din0 ‐ din3) and data output (q), whose function is defined by the sixteen‐bit lut_function parameter. The LUT4 is treated as a black‐box by the synthesis tools. The user may instantiate this block to define specific structures of logic functions.
Lookup Table (LUT) Functions LUT4 Table 4-3: Function Table din3 din2 din1 din0 q 0 0 0 0 lut_function[0] 0 0 0 1 lut_function[1] 0 0 1 0 lut_function[2] 0 0 1 1 lut_function[3] 0 1 0 0 lut_function[4] 0 1 0 1 lut_function[5] 0 1 1 0 lut_function[6] 0 1 1 1 lut_function[7] 1 0 0 0 lut_function[8] 1 0 0 1 lut_function[9] 1 0 1 0 lut_function[10] 1 0 1 1 lut_function[11] 1 1 0 0 lut_function[12] 1 1 0 1 lut_function[13] 1 1 1 0
Chapter 5 – Arithmetic Functions ALU Two Input Adder / Subtractor with Programmable Load a[1:0] b[1:0] d[1:0] load ALU cout s[1:0] cin Figure 5-1: Logic Symbol ALU implements either a two‐bit adder or two‐bit subtractor with adder/subtractor inputs (a[1:0], b[1:0]), load value (d[1:0]), Load Enable (load) and carry‐in (cin) inputs. It generates the sum/difference (s[1:0]) and carry‐out (cout) outputs.
Arithmetic Functions ALU Parameters Table 5-2: Parameters Parameter Defined Values invert_b 1’b0, 1’b1 Default Value 1’b0 invert_b The invert_b parameter defines if the ALU functions as an adder or a subtractor. Setting the invert_b parameter to 1’b0 configures the ALU to perform two’s complement addition of a[1:0] + b[1:0] + cin. Setting the invert_b parameter to 1’b1 configures the ALU to invert the b[1:0] input so that the two’s complement subtraction of a[1:0] ‐ b[1:0] is performed.
Arithmetic Functions ALU VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation LUT4_instance_name : LUT4 generic map (invert_b => ‘0’) port map (s => user_sum, cout => user_carry_out, a => user_a, b => user_b, d => user_d, load => user_load, cin => user_carry_in); Speedster Macro Cell Library www.achronix.
Chapter 6 – Memories BRAM80K 80k-bit Dual-Port Memory addra[15:0] dina[31:0] dinpa[3:0] dinpxa[3:0] wea[3:0] pea rstlatcha rstrega outregcea clka BRAM80K addrb[15:0] dinb[31:0] dinpb[3:0] dinpxb[3:0] web[3:0] peb rstlatchb rstregb outregceb clkb douta[31:0] doutpa[3:0] doutpxa[3:0] doutb[31:0] doutpb[3:0] doutpxb[3:0] Figure 6-1: Logic Symbol The block RAM (BRAM80K) implements a 80k‐bit dual‐ported memory block where each port can be independently configured with respect to size and function.
Memories BRAM80K BRAM80K Pins Table 6-1: BRAM80K Pin Descriptions Name Type dina[31:0], dinb[31:0] input dinpa[3:0], dinpb[3:0] input dinpxa[3:0], dinpxb[3:0] input addra[15:0], addrb[15:0] input Port A(B) read/write address input. Note that the addra, addrb inputs are top justified. See Table 6‐11: BRAM80K Address Bus Mapping (Per Port) wea[3:0], web[3:0] input Port A(B) byte-wide (10-bit) write enable.
Memories BRAM80K Name Type Description douta[31:0], doutb[31:0] Port A(B) data output. For read operations, the douta(doutb) outputs are updated with the memory contents addressed by addra(addrb) if the pea(peb) port enable is active and wea(web) inputs are low.
Memories BRAM80K porta_read_width(portb_read_width) The porta_read_width(portb_read_width) parameter sets the read width for Port A(B). The read width may vary from the write port width, but it must be within the allowable combinations defined in the Memory Organization and Data Input / Output Pin Assignments section. porta_write_width(portb_write_width) The porta_write_width(porta_write_width) parameter sets the write width for Port A(B).
Memories BRAM80K porta_reg_rstval(portb_reg_rstval) The porta_reg_rstval(portb_reg_rstval) parameter defines the active level of the Port A(B) output register reset input. Assigning a value of 1’b0 to porta_reg_rstval(portb_reg_rstval) configures the Port A(B) output register to have an active‐low synchronous reset, while assigning a value of 1’b1 configures the Port A(B) output register to have an active‐high synchronous reset.
Memories BRAM80K porta_srval(portb_srval) The porta_srval(portb_srval) parameter defines the value assigned to the Port A(B) output latch(register if porta_en_out_reg(portb_en_out_reg)=1) at the next active edge of the clock when the Port A(B) latch(register) reset conditions are met. The 40‐bit porta_srval(portb_srval) parameter assignment is dependent on the porta_read_width(portb_read_width).
Memories BRAM80K initpx_00 – initpx_31 The initpx_00 through initpx_31 parameters define the initial contents of the memory contents associated with doutpxa[3:0] and doutpxb[3:0]. Each 256‐bit parameter associated with the BRAM80K memory is defined in the Memory Initialization section. Memory Organization and Data Input / Output Pin Assignments The BRAM80K memory block supports memory widths from one to forty bits wide.
Memories BRAM80K Table 6-8: dina(dinb) bit assignments per porta_write_width(portb_write_width) values porta_write_width, portb_write_width dinpxa[3:0], dinpxb[3:0] dinpa[3:0], dinpb[3:0] dina[31:0], dinb[31:0] 40 user_din[39:36] user_din[35:32] user_din[31:0] 36 4’hx user_din[35:32] user_din[31:0] 32 4’hx 4’hx user_din[31:0] 20 2’bxx,user_din[19:18] 2’bxx,user_din[17:16] 16’hxxxx,user_din[15:0] 18 4’hx user_din[17:16] 16’hxxxx,user_din[15:0] 16 4’hx 4’hx 16’hxxxx,user_din[15:0]
Memories BRAM80K Table 6-10: douta(doutb) bit assignments per porta_read_width(portb_read_width) values porta_read_width, portb_read_width doutpxa[3:0], doutpxb[3:0] doutpa[3:0], doutpb[3:0] douta[31:0], doutb[31:0] 40 user_dout[39:36] user_dout[35:32] user_dout[31:0] 36 4’hx user_dout[35:32] user_dout[31:0] 4’hx 4’hx 32 20 user_dout[31:0] 2’bxx,user_dout[19:18] 2’bxx,user_dout[17:16] 16’hxxxx,user_dout[15:0] 18 4’hx user_dout[17:16] 16’hxxxx,user_dout[15:0] 16 4’hx 4’hx 16’hxxxx
Memories BRAM80K Table 6-12: Mapping of Word Sizes to the Native 2048x40 Memory Locations Port Extended Width Parity Bits Parity Bits Data Bits 40 0 0 0 36 n/a 0 0 32 20 18 n/a 1 0 n/a 0 1 0 1 0 1 0 1 0 1 0 16 n/a 10 3 2 1 0 3 2 1 0 9 n/a 3 2 1 0 3 2 1 0 3 2 1 0 8 n/a 5 7 6 5 4 3 2 1 0 7 3 6 5 2 4 3 1 2 1 0 4 n/a 7 6 5 4 3 2 1 0 2 n/a 15 14 13 12 11 10 9 1 n/a 33222222222211111111119876543210 1098765432109876543210 8 7 6 0 5 4 3 2
Memories BRAM80K Table 6-13: BRAM Output Function Table for Latched Mode (Assumes active-high clock, port enable, and latch reset value) Operation pea wea rstlatcha porta_write_mode clka douta (doutb) (peb) (web) (rstlatchb) (portb_write_mode) (clkb) Hold X X X X X douta_previous (doutb_previous) Hold 0 X X X douta_previous (doutb_previous) Reset Output 1 X 1 X porta_srval (portb_srval) Read 1 0 0 X mem[addra] (mem[addrb]) Write 1 1 0 “write-first” dina (dinb)
Memories BRAM80K correct data at both output ports. In this case, the data corruption will not be noticed by the circuit until the the corrupted memory location is later read.
Memories BRAM80K Figure 6-5: No-Change, Latched Mode Timing Diagram Figure 6-6: No-Change, Registered Mode Timing Diagram Support for Read-First (Read-Before-Write) Memory Operations The BRAM80K memory does not directly support read‐first or read‐before‐write mode of operation. If this behavior is detected by synthesis, a warning will be issued in the synthesis log file and a register file will be synthesized.
Memories BRAM80K When the BRAM80K memory is configured with port widths of 9, 18, or 36 bits wide, the initial memory contents may be defined by initializing the 256 256‐bit parameters initd_000 through initd_255 and the 32 256‐bit parameters initp_00 through initp_31.
Memories BRAM80K BRAM80K Verilog Instantiation Template BRAM80K #( .porta_read_width(40), .porta_write_width(40), .porta_write_mode("write_first"), .porta_clock_polarity("rise"), .porta_en_out_reg(1'b0), .porta_regce_priority("rstreg"), .porta_peval(1'b1), .porta_reg_rstval(1'b1), .porta_latch_rstval(1'b1), .porta_initval(40'h0), .porta_srval(40'h0), .portb_read_width(40), .portb_write_width(40), .portb_write_mode("write_first"), .portb_clock_polarity("rise"), .portb_en_out_reg(1'b0), .
Memories BRAM80K .initd_019(256'h0), .initd_020(256'h0), .initd_021(256'h0), .initd_022(256'h0), .initd_023(256'h0), .initd_024(256'h0), .initd_025(256'h0), .initd_026(256'h0), .initd_027(256'h0), .initd_028(256'h0), .initd_029(256'h0), .initd_030(256'h0), .initd_031(256'h0), .initd_032(256'h0), .initd_033(256'h0), .initd_034(256'h0), .initd_035(256'h0), .initd_036(256'h0), .initd_037(256'h0), .initd_038(256'h0), .initd_039(256'h0), .initd_040(256'h0), .initd_041(256'h0), .initd_042(256'h0), .
Memories BRAM80K .initd_065(256'h0), .initd_066(256'h0), .initd_067(256'h0), .initd_068(256'h0), .initd_069(256'h0), .initd_070(256'h0), .initd_071(256'h0), .initd_072(256'h0), .initd_073(256'h0), .initd_074(256'h0), .initd_075(256'h0), .initd_076(256'h0), .initd_077(256'h0), .initd_078(256'h0), .initd_079(256'h0), .initd_080(256'h0), .initd_081(256'h0), .initd_082(256'h0), .initd_083(256'h0), .initd_084(256'h0), .initd_085(256'h0), .initd_086(256'h0), .initd_087(256'h0), .initd_088(256'h0), .
Memories BRAM80K .initd_111(256'h0), .initd_112(256'h0), .initd_113(256'h0), .initd_114(256'h0), .initd_115(256'h0), .initd_116(256'h0), .initd_117(256'h0), .initd_118(256'h0), .initd_119(256'h0), .initd_120(256'h0), .initd_121(256'h0), .initd_122(256'h0), .initd_123(256'h0), .initd_124(256'h0), .initd_125(256'h0), .initd_126(256'h0), .initd_127(256'h0), .initd_128(256'h0), .initd_129(256'h0), .initd_130(256'h0), .initd_131(256'h0), .initd_132(256'h0), .initd_133(256'h0), .initd_134(256'h0), .
Memories BRAM80K .initd_157(256'h0), .initd_158(256'h0), .initd_159(256'h0), .initd_160(256'h0), .initd_161(256'h0), .initd_162(256'h0), .initd_163(256'h0), .initd_164(256'h0), .initd_165(256'h0), .initd_166(256'h0), .initd_167(256'h0), .initd_168(256'h0), .initd_169(256'h0), .initd_170(256'h0), .initd_171(256'h0), .initd_172(256'h0), .initd_173(256'h0), .initd_174(256'h0), .initd_175(256'h0), .initd_176(256'h0), .initd_177(256'h0), .initd_178(256'h0), .initd_179(256'h0), .initd_180(256'h0), .
Memories BRAM80K .initd_203(256'h0), .initd_204(256'h0), .initd_205(256'h0), .initd_206(256'h0), .initd_207(256'h0), .initd_208(256'h0), .initd_209(256'h0), .initd_210(256'h0), .initd_211(256'h0), .initd_212(256'h0), .initd_213(256'h0), .initd_214(256'h0), .initd_215(256'h0), .initd_216(256'h0), .initd_217(256'h0), .initd_218(256'h0), .initd_219(256'h0), .initd_220(256'h0), .initd_221(256'h0), .initd_222(256'h0), .initd_223(256'h0), .initd_224(256'h0), .initd_225(256'h0), .initd_226(256'h0), .
Memories BRAM80K .initd_249(256'h0), .initd_250(256'h0), .initd_251(256'h0), .initd_252(256'h0), .initd_253(256'h0), .initd_254(256'h0), .initd_255(256'h0), .initp_00(256'h0), .initp_01(256'h0), .initp_02(256'h0), .initp_03(256'h0), .initp_04(256'h0), .initp_05(256'h0), .initp_06(256'h0), .initp_07(256'h0), .initp_08(256'h0), .initp_09(256'h0), .initp_10(256'h0), .initp_11(256'h0), .initp_12(256'h0), .initp_13(256'h0), .initp_14(256'h0), .initp_15(256'h0), .initp_16(256'h0), .initp_17(256'h0), .
Memories BRAM80K .initpx_07(256'h0), .initpx_08(256'h0), .initpx_09(256'h0), .initpx_10(256'h0), .initpx_11(256'h0), .initpx_12(256'h0), .initpx_13(256'h0), .initpx_14(256'h0), .initpx_15(256'h0), .initpx_16(256'h0), .initpx_17(256'h0), .initpx_18(256'h0), .initpx_19(256'h0), .initpx_20(256'h0), .initpx_21(256'h0), .initpx_22(256'h0), .initpx_23(256'h0), .initpx_24(256'h0), .initpx_25(256'h0), .initpx_26(256'h0), .initpx_27(256'h0), .initpx_28(256'h0), .initpx_29(256'h0), .initpx_30(256'h0), .
Memories BRAM80K .rstregb(user_rstregb), .outregceb(user_outregceb), .clkb(user_clkb), .doutb(user_doutb), .doutpb(user_doutpb), .doutpxb(user_doutpxb)); BRAM80K VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Memories BRAM80K initd_007 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_008 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_009 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_010 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_011 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_012 => X"0000000000000000000000000000000000000000000000000000000000000000", i
Memories BRAM80K initd_062 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_063 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_064 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_065 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_066 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_067 => X"0000000000000000000000000000000000000000000000000000000000000000", i
Memories BRAM80K initd_117 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_118 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_119 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_120 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_121 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_122 => X"0000000000000000000000000000000000000000000000000000000000000000", i
Memories BRAM80K initd_172 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_173 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_174 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_175 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_176 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_177 => X"0000000000000000000000000000000000000000000000000000000000000000", i
Memories BRAM80K initd_227 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_228 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_229 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_230 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_231 => X"0000000000000000000000000000000000000000000000000000000000000000", initd_232 => X"0000000000000000000000000000000000000000000000000000000000000000", i
Memories BRAM80K initp_26 => X"0000000000000000000000000000000000000000000000000000000000000000", initp_27 => X"0000000000000000000000000000000000000000000000000000000000000000", initp_28 => X"0000000000000000000000000000000000000000000000000000000000000000", initp_29 => X"0000000000000000000000000000000000000000000000000000000000000000", initp_30 => X"0000000000000000000000000000000000000000000000000000000000000000", initp_31 => X"0000000000000000000000000000000000000000000000000000000000000000", initpx_
Memories BRAM80K addrb => user_addrb , dinb => user_dinb , dinpb => user_dinpb , dinpxb => user_dinpxb , web => user_web , peb => user_peb , rstlatchb => user_rstlatchb , rstregb => user_rstregb , outregceb => user_outregceb , clkb => user_clkb , doutb => user_doutb , doutpb => user_doutpb , doutpxb => user_doutpxb); Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 118
Memories BRAM80KFIFO BRAM80KFIFO 80k-bit FIFO Memory din[31:0] dinp[3:0] dinpx[3:0] wren wrrst wrclk BRAM80KFIFO dout[31:0] doutp[3:0] doutpx[3:0] rden rdclk rdrst empty full almost_empty almost_full write_err read_err outregce rstreg wrcount[16:0] rdcount[16:0] Figure 6-7: Logic Symbol The BRAM80KFIFO implements a 80k‐bit FIFO memory block utilizing the embedded BRAM80K blocks with dedicated pointer and flag circuitry.
Memories BRAM80KFIFO Table 6-15: BRAM80KFIFO Pin Description Type Clock Domain din[31:0] input wrclk Write port data input. dinp[3:0] input wrclk Write port parity input (may be used for data). dinpx[3:0] input wrclk Write port extended parity input (may be used for data). wren input wrclk Write enable (active-high). Data is written into the FIFO at the next active edge of the write clock when wren is driven high, as long as the full flag is not asserted.
Memories BRAM80KFIFO Parameters Table 6-16: BRAM80KFIFO Parameters Parameter Defined Values Default Value sync_mode 1’b0, 1’b1 1’b0 write_width 1, 2, 4, 5, 8, 9, 10, 16, 18, 20, 32, 36, 40 40 read_width 1, 2, 4, 5, 8, 9, 10, 16, 18, 20, 32, 36, 40 40 fwft 1’b0, 1’b1 1’b0 en_out_reg 1’b0, 1’b1 1’b1 reg_initval 40-bit hexadecimal number 40’h0 reg_srval 40-bit hexadecimal number 40’h0 1’b0, 1’b1 1’b1 reg_rstval regce_priority “rstreg”, “regce” wrrst_rstval “rstreg” 1’b0, 1’b1
Memories BRAM80KFIFO Table 6-17: FIFO write_width versus Maximum Write Depth write_width FIFO Write Depth fwft = 1’b0 FIFO Write Depth fwft = 1’b1 40 2048 2049 36 2048 2049 32 2048 2049 20 4096 4097 18 4096 4097 16 4096 4097 10 8192 8193 9 8192 8193 8 8192 8193 5 16384 16385 4 16384 16385 2 32768 32769 1 65536 65537 Table 6-18: din, dinp, dinpx bit assignments per write_width values write_width dinpx[3:0] dinp[3:0] din[31:0] 40 user_din[39:36] user_din[35:
Memories BRAM80KFIFO Table 6-19: FIFO read_width versus Maximum Read Depth read_width FIFO Read Depth fwft = 1’b0 FIFO Read Depth fwft = 1’b1 40 2048 2049 36 2048 2049 32 2048 2049 20 4096 4097 18 4096 4097 16 4096 4097 10 8192 8193 9 8192 8193 8 8192 8193 5 16384 16385 4 16384 16385 2 32768 32769 1 65536 65537 Table 6-20: dout bit assignments per read_width values read_width doutpx[3:0] doutp[3:0] dout[31:0] 40 user_dout[39:36] user_dout[35:32] user_dout
Memories BRAM80KFIFO Table 6-21: Valid Read Width Versus Write Width Combinations per port for n x 5 width modes Port Write Width Port Read Width 2kx40 4kx20 8kx10 16kx5 Other 40 – 20 – 10 – 5 – Table 6-22: Valid Read Width Versus Write Width Combinations per port for n x 9 width modes Port Write Width Port Read Width 2kx36 4kx18 8kx9 Other 36 – 18 – 9 – Table 6-23: Valid Read Width Versus Write Width C
Memories BRAM80KFIFO reg_initval The reg_initval parameter defines the 40‐bit initial value on the output of the FIFO upon application of power to the device. The 40‐bit reg_initval parameter assignment is dependent on the read_width parameter value. The association of the of the reg_initval parameter values to the dout,doutp,doutpx bits is assigned according to Table 6‐24: Relationship of reg_initval bit positions to dout,doutp,doutpx. The default value of reg_initval is 40’h0.
Memories BRAM80KFIFO Table 6-25: Relationship of reg_srval bit positions to dout,doutp,doutpx read_width doutpx reg_srval[39:36] doutp reg_srval[35:32] dout reg_srval[31:0] 40 user_srval[39:36] user_srval[35:32] user_srval[31:0] 36 4’hx user_srval[35:32] user_srval[31:0] 32 4’hx 4’hx user_srval[31:0] 20 2’bxx,user_srval[19:18] 2’bxx,user_srval[17:16] 16’hxxxx,user_srval[15:0] 18 4’hx 2’bxx,user_srval[17:16] 16’hxxxx,user_srval[15:0] 16 4’hx 4’hx 16’hxxxx,user_srval[15:0] 10 3
Memories BRAM80KFIFO inputs. Alternatively, the user may also program the reset of the Write Pointer and Read Pointer independently of each other. For example, the user may program the FIFO reset inputs to act independently of each other so that the Read Pointer is reset exclusively by the rdrst input to allow the contents of a previously written FIFO to be reread. Note that as a result of the Write Pointer reset, the flag outputs are also updated.
Memories BRAM80KFIFO Table 6-27: Reset Usage Model for wrrst and rdrst Inputs Required Required wrrst_input_mode rdrst_input_mode assignment assignment Use Model Required wrrst and rdrst connections A single reset in the rdclk domain resets both the read and write pointers. The user reset is connected to the rdrst input. The wrrst signal is tied inactive. 2’b11 2’b00 A single reset in the wrclk domain resets both the read and write pointers. The user reset is connected to the wrrst input.
Memories BRAM80KFIFO event when transferring the Write Pointer across clock domains. As an example, setting wrptr_sync_stages to 2’b00 configures the write pointer synchronization circuit to have two back‐to‐back registers in the Write Pointer Synchonizer. The default value of the wrptr_sync_stages parameter is 2’b00.
Memories BRAM80KFIFO rdrst_sync_stages The rdrst_sync_stages parameter defines the number of stages of registers used to synchronize the rdrst input pin to the wrclk clock domain if the rdrst signal is used by the Write Pointer Reset. The value of the rdrst_sync_stages parameter is only used if the wrrst_input_mode is set to 2’b10 or 2’b11.
Memories BRAM80KFIFO rdcount_sync_mode The rdcount_sync_mode parameter defines whether the read counter (rdcount) output is synchonous to the rdclk clock input. Assigning a value of 1’b0 to rdcount_sync_mode configures therdcount output to be synchonized to the wrclk clock. Assigning a value of 1’b1 to rdcount_sync_mode configures the rdcount output to be synchonized to the rdclk clock. The default value of the rdcount_sync_mode parameter is 1’b1.
Memories BRAM80KFIFO Table 6-34: Condition to Assert almost_empty Flag based on afull_offset Parameter Assignment Condition when almost_empty flag is asserted Mode Condition when almost_empty flag is deasserted sync_mode = 1’b0, fwft = 1’b0 aempty_offset or fewer words remain in the FIFO. There are at least (aempty_offset +1) words in the FIFO. sync_mode = 1’b0, fwft = 1’b1 (aempty_offset + 1) or fewer words remain in the FIFO.
Memories BRAM80KFIFO Read and Write Count Outputs Write Count Output The Write Count (wrcount) output of the FIFO shows the value of the Write Pointer. The wrcount may be synchronized to either the wrclk or rdclk clock domains by setting the wrcount_sync_mode parameter bit. Setting the wrcount_sync_mode parameter to 1’b1 outputs the wrcount directly from the Write Pointer (synchronous to the wrclk clock).
Memories BRAM80KFIFO Status Flags Empty Flag The Empty (empty) flag is asserted after the FIFO is reset or when all of the data has been read from the FIFO. The Empty flag is synchronous to the rdclk clock domain. Further attempts to read the FIFO when the Empty flag is asserted will depend upon the en_rd_when_empty parameter.
Memories BRAM80KFIFO Read Error Flag The Read Error (read_err) flag is asserted in the following rdclk clock cycle when the user tries to read the FIFO while the Empty Flag is high and the Enable Read When Empty (en_rd_when_empty) parameter is set to 1’b0. The Read Error flag is undefined when the Enable Read When Empty parameter is set to 1’b1. Flag Latency The empty, full, almost_empty, and almost_full flags are calculated based on comparisons between the FIFO write pointer and the FIFO read pointer.
Memories BRAM80KFIFO Flag Latency in Terms of Read Clock Cycles and Table 6‐38: Full and Almost Full Flag Latency in Terms of Write Clock Cycles show the latency for the FIFO flag calculations.
Memories BRAM80KFIFO Operation regce_priority rstreg outregce rdclk dout Reset Output “regce” 1 1 reg_srval FIFO Operational Modes The FIFO macro supports both single clock synchronous (same clock connected to wrclk and rdclk inputs without any phase offset between the two clocks) and dual clock asynchronous (two unrelated clocks or two related clocks) modes of operation. For synchronous operation, both the wrclk and rdclk inputs must be connected to the same clock net.
Memories BRAM80KFIFO FIFO may be configured with or without the output register enabled. When the output register is disabled, there is a single cycle of latency for the FIFO read operations, but it has a longer clock to output delay of the output data. To reduce the clock to out delay of the synchronous FIFO, the output register may be enabled (en_out_reg = 1’b1), but the FIFO data output has an additional cycle of latency.
Memories BRAM80KFIFO Figure 6-12: Basic Mode FIFO Reset Timing Diagram A B C D E F G wrclk rdclk wren rden wrrst, rdrst empty almost_empty full almost_full Note: This timing diagram assumes: 1. User reset signal connected to wrrst and rdrst inputs 2. wrrst and rdrst configured as active-high wrrst_rstval = 1’b1, rdrst_rstval = 1’b1. Event A : The user must disable the wren signal during the reset operation. Event B : The user must disable the rden signal during the reset operation.
Memories BRAM80KFIFO Figure 6‐9: Read and Write Pointer Reset Input Selection Block Diagram shows the block diagram of the FIFO Reset Selection circuitry. The circuits to configure the Read Pointer and Write Pointer resets are identical. The wrrst_sync_stages(rdrst_sync_stages) parameter configures the depth of the wrrst(rdrst) synchronizer from two to five stages according to the definitions in Table 6‐28: Mapping wrrst_sync_stages Parameter Settings to Synchro‐ nization Stage Depth.
Memories BRAM80KFIFO Figure 6-13: Reset Behavior Timing Diagram (Requires sync wrrst ) A B C D E F G C wrclk rdclk wren rden wrrst empty almost_empty full almost_full Note: This timing diagram assumes: 1. wrrst input resets both the Write Pointer and the Read Pointer 2. Write Pointer sychronously reset by wrrst input (wrrst_input_mode = 2’b00) 3. Reset Sychronizer sychronizes wrrst input with two stages of registers (rdrst_input_mode = 2’b11, wrrst_sync_stages = 2’b00) 4.
Memories BRAM80KFIFO Writing an Empty Asynchronous FIFO (sync_mode = 1’b0) Figure 6-14: Writing an Empty Asynchronous FIFO (sync_mode = 1’b0) A B C D wrclk rdclk wren rden wrd 0 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 wrd 6 din dout (fwft = 1’b0) Previous Read Word wrd 0 empty (fwft = 1’b0) dout (fwft = 1’b1) Previous Read Word wrd 0 wrd 1 empty (fwft = 1’b1) almost_empty (fwft = 1’b0) almost_empty (fwft = 1’b1) Note: This timing diagram assumes: 1.
Memories BRAM80KFIFO Writing to an Almost Full FIFO (en_wr_when_full = 1’b0) Figure 6-16: Writing to an Almost Full FIFO (en_wr_when_full = 1’b0) A B C D wrclk rdclk wren rden wrd 2042 wrd 2043 wrd 2044 wrd 2045 wrd 2046 wrd 2047 wrd 2048 din almost_full full write_err Note: This timing diagram assumes: 1. Almost Full Offset programmed for 5 40-bit words (aempty_offset = 17’h00004) 2. wptr_sync_stages = 2’b00 3.
Memories BRAM80KFIFO Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0) Figure 6-18: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0) A B C D E F G wrclk rdclk wren wrd 4 din wrd 5 rden wrd 0 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 dout almost_empty empty read_err Note: This timing diagram assumes: 1. Almost Empty Offset programmed for 6 40-bit words (aempty_offset = 17’h00005) 2. wptr_sync_stages = 2’b00 3. en_rd_when_empty = 1’b0 4.
Memories BRAM80KFIFO Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b1) Figure 6-19: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b1) A B C D E F G wrclk rdclk wren wrd 4 din wrd 5 rden wrd 0 dout wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 almost_empty empty read_err Note: This timing diagram assumes: 1. Almost Empty Offset programmed for 6 40-bit words (aempty_offset = 17’h00004) 2. wptr_sync_stages = 2’b00 3. en_rd_when_empty = 1’b0 4.
Memories BRAM80KFIFO Writing and Reading a Mixed-Width FIFO Figure 6-21: Writing and Reading a Mixed-Width FIFO wrclk rdclk wren rden word 0 word 1 din word 0[15:0] word 0[31:16] word 1[15:0] word 1[31:16] dout empty almost_empty Note: This timing diagram assumes: 1. write_width = 32, read_width = 16 2. wptr_sync_stages = 2’b00 3. sync_mode = 1’b0 4.
Memories BRAM80KECC BRAM80KECC 80k-bit Simple Dual-Port Memory with Error Correction BRAM80KECC dout[31:0] doutp[3:0] doutpx[3:0] din[31:0] dinp[3:0] dinpx[3:0] wraddr[10:0] wren wrclk sbit_error dbit_error rdaddrecc[10:0] rdaddr[10:0] rden rstreg outregce rdclk enc_parity[6:0] Figure 6-22: Logic Symbol The BRAM80KECC implements an 2kx32 simple dual‐ported memory block with error correction codes (ECC).
Memories BRAM80KECC BRAM80KECC Pins Table 6-41: BRAM80KECC Pin Descriptions Name Type Description din[31:0] input Write Port Data Input. dinp[3:0] input Write Port Parity Input (may be used for data). dinpx[3:0] input Write Port Extended Parity input (may be used for data). wraddr[10:0] input Write Address. wren input Write Enable (active-high). wrclk input Write Clock (programmable, default rising edge = 1’b1). rdaddr[10:0] input Read Address.
Memories BRAM80KECC en_out_reg The en_out_reg parameter enables the register at the output of the BRAM80KECC block. A value of 1’b0 disables the output register. When the output register is enabled by setting the en_out_reg to 1’b1, there is an additional cycle of latency for each read operation. The default value of the en_out_reg parameter is 1’b0. reg_initval The reg_initval parameter defines the 40‐bit initial value on the output of the BRAM80KECC upon application of power to the device.
Memories BRAM80KECC decoder_enable The decoder_enable parameter defines if the ECC decoder circuitry is selected or bypassed. Setting decoder_enable to 1’b1 enables the ECC decoder for normal operation. Setting decoder_enable to 1’b0 disables the ECC decoder circuitry and allows the dout, doutp, and doutpx memory outputs to be routed to the output ports without error correction. The default value of the decoder_enable parameter is 1’b1.
Memories BRAM80KECC BRAM80KECC Modes of Operation There are three modes of operation for the BRAM80KECC block defined by the encoder_enable and decoder_enable parameter shown in Table 6‐45: BRAM80KECC Modes of Operation.
Memories BRAM80KECC Figure 6-24: ECC Write Operation Timing Diagram wrclk wren wraddr[10:0] waddr 0 waddr 1 waddr 2 waddr 3 waddr 4 waddr 5 waddr 6 din[31:0] din 0 din 1 din 2 din 3 din 4 din 5 din 6 dinpx[3:0] (Decode-Only) dinp 0 dinp 1 dinp 2 dinp 3 dinp 4 dinp 5 dinp 6 dinp[3:0] (Decode-Only) dinpx 0 dinpx 1 dinpx 2 dinpx 3 dinpx 4 dinpx dinpx 6 enc_parity[6:0] encpar 0 encpar 1 encpar 2 encpar 3 encpar 4 encpar 5 encpar 6 Figure 6-25: ECC Read Operation Timing Diagram rdcl
Memories BRAM80KECCFIFO BRAM80KECCFIFO 80k-bit FIFO Memory with Error Correction din[31:0] dinp[3:0] dinpx[3:0] wren wrrst wrclk BRAM80KECCFIFO dout[31:0] doutp[3:0] doutpx[3:0] empty full almost_empty almost_full write_err read_err rden rdclk rdrst outregce rstreg sbit_error dbit_error rdaddrecc[10:0] Figure 6-27: Logic Symbol The BRAM80KECCFIFO implements a 2k deep, 32‐bit wide FIFO memory block utilizing the embedded BRAM80K blocks with dedicated pointer and flag circuitry.
Memories BRAM80KECCFIFO Table 6-46: BRAM80KECCFIFO Pin Description Type Clock Domain din[31:0] input wrclk Write port data input. dinp[3:0] input wrclk Write port parity input (may be used for data). dinpx[3:0] input wrclk Write port extended parity input (may be used for data). wren input wrclk Write enable (active-high). Data is written into the FIFO at the next active edge of the write clock when wren is driven high, as long as the full flag is not asserted.
Memories BRAM80KECCFIFO Parameters Table 6-47: BRAM80KECCFIFO Parameters Parameter Defined Values Default Value sync_mode 1’b0, 1’b1 1’b0 en_out_reg 1’b0, 1’b1 1’b1 reg_initval 40-bit hexadecimal number 40’h0 reg_srval 40-bit hexadecimal number 40’h0 reg_rstval 1’b0, 1’b1 1’b1 “rstreg”, “regce” regce_priority “rstreg” 1’b0, 1’b1 1’b1 wrrst_input_mode 2’b00, 2’b01, 2’b10, 2’b11 2’b10 wrrst_sync_stages 2’b00, 2’b01, 2’b10, 2’b11 2’b00 wrptr_sync_stages 2’b00, 2’b01, 2’b10, 2’b
Memories LRAM640 LRAM640 640-bit (64x10) Simple-Dual-Port Memory wraddr[5:0] din[9:0] wren wclk LRAM640 dout[9:0] rdaddr[5:0] rstregn outregce rdclk Figure 6-29: Logic Symbol The Logic RAM (LRAM640) implements a 640‐bit memory block with one write port and one read port. The LRAM640 can be configured as either a 64x10 simple dual‐port (1 write port, 1 read port) RAM or a 64x10 single port (1 read/write port) RAM. The LRAM640 has a synchronous write port.
Memories LRAM640 LRAM640 Pins Table 6-48: LRAM640 Pin Descriptions Name Type Description wraddr[5:0] input Write Port Address Input. din[9:0] input Write Port Data Input. wren input Write Port Enable. (active-high) When the Write Port Enable signal is asserted, the data present on the Write Port Data Input (din[9:0]) is written into the memory location addressed by the Write Port Address input (wraddr[5:0]) at the next active edge of wrclk. wrclk input Write Port Clock.
Memories LRAM640 write_clock_polarity The write_clock_polarity parameter is used to set the active edge of the wrclk clock. A value of “rise” corresponds to an active rising edge assignment while “fall” corresponds to an active falling edge assignment. The default value of the write_clock_polarity parameter is “rise”. read_clock_polarity The read_clock_polarity parameter is used to set the active edge of the rdclk clock.
Memories LRAM640 Simultaneous Memory Operations Memory operations may be performed simultaneously from both sides of the memory, however there is a restriction with memory collisions. A memory collision is defined as the condition where both of the ports access the same memory address within the same clock cycle (both ports connected to the same clock), or within a TBD ps window (if each port is connected to a different clock).
Memories LRAMFIFO LRAMFIFO LRAM-Based 64-Word FIFO Memory din[width - 1:0] LRAMFIFO dout[width - 1:0] wren wrclk empty full almost_empty almost_full write_err read_err rden rstn rdclk Figure 6-31: Logic Symbol The LRAMFIFO implements a 64 word by n‐bit FIFO memory block utilizing the embedded LRAM blocks and LUTs. The LRAMFIFO can be configured to support a variety of widths in increments of one bit. The read and write clocks may be either synchronous or asynchronous with respect to each other.
Memories LRAMFIFO Table 6-50: LRAMFIFO Pin Description Type Clock Domain din[width-1:0] input wrclk Write port data input. wren input wrclk Write enable (active-high). Data is written into the FIFO at the next rising edge of the write clock when wren is driven high, as long as the full flag is not asserted. wrclk input wrclk Write clock. (rising edge based). rstn input async. FIFO reset (active-low).
Memories LRAMFIFO ptr_sync_mode The ptr_sync_mode parameter is used to bypass the synchronization circutry between the read and write ports when both ports are connected to the same clock. If both the wrclk and rdclk clock inputs are connected to the same clock, the user may set the ptr_sync_mode parameter to 1’b1 to allow faster updates to the status flags (empty, full, etc.). Note that when ptr_sync_mode is set to 1’b1, the two clocks have to be connected to the same clock net.
Memories LRAMFIFO transferring the Read Pointer across clock domains. As an example, setting rdptr_sync_stages to 2’b00 configures the read pointer synchronization circuit to have two back‐to‐back registers in the Read Pointer Synchonizer. The default value of the rdptr_sync_stages parameter is 2’b00.
Memories LRAMFIFO Figure 6-35: Write Pointer Reset Input Selection Block Diagram wrrst_sync_stages rstn Write Reset Synchronizer dq dq dq dq dq 1 00 01 10 11 0 Write Pointer Reset rst_sync_mode rdclk rdrst_sync_stages The rdrst_sync_stages parameter defines the number of stages of registers used to synchronize the rstn input pin to the wrclk clock domain. The value of the rdrst_sync_stages parameter is only used if the rst_sync_mode is set to 1’b0.
Memories LRAMFIFO Table 6-56: Condition to Assert almost_full Flag based on afull_offset Parameter Assignment Condition when Condition when almost_full flag is almost_full flag is asserted deasserted afull_offset or fewer empty loca- There are at least (afull_offset +1) empty tions remain in the FIFO. locations remaining in the FIFO. aempty_offset The aempty_offset parameter defines the word depth at which the FIFO almost_empty changes.
Memories LRAMFIFO of blind writes to the FIFO that can be made without monitoring the full flag. For example, if the afull_offset parameter is set to 7’h04 and the almost_full flag is deasserted, the user is guaranteed that there are at least five empty locations in the FIFO. The user may write all five words without monitoring the full flag and be guaranteed that these words will be written to the FIFO and the write_err flag will not be asserted.
Memories LRAMFIFO For example, the empty flag is computed from the Synchronized Write Pointer and the Read Pointer. The write pointer incurs an additional delay of two to five rdclk cyles (set by the wrptr_sync_stages parameter) before it is used to calculate the empty flag. Therefore, the empty flag will not transition from the empty to non‐empty state for a minimum of two rdclk cycles after the first write to the FIFO occurs. A similar delay occurs for the almost_empty flag as well.
Memories LRAMFIFO Synchronous FIFO Mode (ptr_sync_mode = 1’b1) The synchronous FIFO standard mode has the advantage that there is no latency in the flag calculations, so the flags represent the exact state of the FIFO. For synchrous operation, both wrclk and rdclk must be tied to the same clock signal. FIFO Operations Asynchronous FIFO Mode Reset Operation Two options are available to the user with regard to resetting the FIFO. For asychronous FIFO Reset, the user set rst_sync_mode to 1’b0.
Memories LRAMFIFO Writing an Empty Asynchronous FIFO (ptr_sync_mode = 1’b0) Figure 6-38: Writing an Empty Asynchronous FIFO (ptr_sync_mode = 1’b0) A B C D wrclk rdclk wren rden wrd 0 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 wrd 6 din dout Previous Read Word wrd 0 empty almost_empty Note: This timing diagram assumes: 1. Almost Empty Offset programmed for 5 40-bit words (aempty_offset = 17’h00005) 2. wptr_sync_stages = 2’b00 3. ptrsync_mode = 1’b0 Event A : Begin writing 7 words to the FIFO.
Memories LRAMFIFO Writing to an Almost Full FIFO Figure 6-40: Writing to an Almost Full FIFO A B C D wrclk rdclk wren rden wrd 2042 wrd 2043 wrd 2044 wrd 2045 wrd 2046 wrd 2047 wrd 2048 din almost_full full write_err Note: This timing diagram assumes: 1. Almost Full Offset programmed for 5 10-bit words (aempty_offset = 7’h04) 2. wptr_sync_stages = 2’b00 Event A : Finish writing 65 words to the FIFO. Event B : The almost_full flag is asserted.
Chapter 7 – Multipliers BMACC56 28 x 28 Multiplier / Accumulator a[27:0] ce_a rst_a BMACC56 b[27:0] ce_b rst_b cascade_out[55:0] cout dout[55:0] cin ce_cin rst_cin sub ce_sub rst_sub mask_adda ce_mask_adda rst_mask_adda ce_dout rst_dout cascade_in[55:0] clk Figure 7-1: Logic Symbol The Multiplier / Accumulator (BMACC56) block implements a signed 28x28 multiplier followed by an optional accumulator block. The multiplier produces a 56‐bit adder result which is fed into the 56‐bit accumulator.
Multipliers BMACC56 cascade_in[55:0] 56 56 1 mask_adda d q ce_mask_adda ce r rst_mask_adda a[27:0]:b[27:0] rst_a multout[55:0] b[27:0] ce_b d q d q ce r rst_b sub ce_sub rst_sub cin ce_cin rst_cin d q ce r 0 1 d q ce r 0 1 cout d q ce r dout d q ce dout[55:0] r cout addb mult [55:0] 28 cascade_out[55:0] adda 28 d q ce r a[27:0] ce_a Signed add/sub sub cin ce_dout rst_dout clk clk_int Figure 7-2: BMACC56 Block Diagram Table 7-1: I/O Count Speedster22i Macro Cell Library
Multipliers BMACC56 BMACC56 Pins Table 7-2: BMACC56 Pin Description Name Type Description a[27:0] input Data Input A. Data Input A is a 28-bit two’s complement signed input, where bit 27 is the most significant bit. In subtraction mode, Data Input A is the minuend. b[27:0] input Data Input B. Data Input B is a 28-bit two’s complement signed input, where bit 27 is the most significant bit. In subtraction mode, Data Input B is the subtrahend. sub input Subtract.
Multipliers BMACC56 Name Type Description input Data Input B Register Reset (active-low). Asserting input rst_b performs a synchronous reset of the Data Input b register upon the next active edge of the clock, and will set the register to the value defined by the rst_value_b parameter. input Subtract Input Register Reset (active-low).
Multipliers BMACC56 Parameters Table 7-3: BMACC56 Parameters Parameter Defined Values Default Value init_a 28-bit hexadecimal value 28’h0 init_b 28-bit hexadecimal value 28’h0 init_sub 1’b0,1’b1 1’b0 init_cin 1’b0,1’b1 1’b0 1’b0,1’b1 1’b0 init_dout 56-bit hexadecimal value 56’h0 init_cout 1’b0,1’b1 1’b0 rst_value_a 28-bit hexadecimal value 28’h0 rst_value_b init_mask_adda 28-bit hexadecimal value 28’h0 rst_value_sub 1’b0,1’b1 1’b0 rst_value_cin 1’b0,1’b1 1’b0 rst_value
Multipliers BMACC56 init_a The init_a parameter defines the power‐up default value of the Data Input A Input Register. The init_a parameter defaults to the value 28’h0. init_b The init_b parameter defines the power‐up default value of the Data Input B Input Register. The init_b parameter defaults to the value 28’h0. init_sub The init_sub parameter defines the power‐up default value of the Subtract Input Register. The init_sub parameter defaults to the value 1’b0.
Multipliers BMACC56 rst_value_mask_adda The rst_value_mask_adda parameter defines the value assigned to the Adda Mask Input Register when the rst_mask_adda input is asserted and there is active edge of the clock. The rst_value_mask_adda parameter defaults to the value 1’b0. rst_value_dout The rst_value_dout parameter defines the value assigned to the Data Out Output Register when the rst_dout input is asserted and there is active edge of the clock.
Multipliers BMACC56 regce_priority_dout The regce_priority_dout parameter defines the priority of the ce_dout clock enable input relative to the rst_dout reset input during an assertion of the rst_dout reset input on the Dout Output Register and Cout Output Register. Setting regce_priority_dout to “rstreg” allows the Dout Output Register and Cout Output Register to be set/reset at the next active edge of the clock without requiring the ce_dout clock enable input to be active.
Multipliers BMACC56 sel_cin The sel_cin parameter defines what is routed to the cin input of the add/sub block. The cin input may be selected from the registered or non‐registered cin input, or forcing it to a constnat value of 0 or 1.The sel_cin parameter defaults to the value 2’b00. Table 7-4: Add/Sub Block Carry Input Assignment sel_cin Add/Sub Block Cin Assignment 2’b00 Select the cin input to drive the add/sub cin input.
Multipliers BMACC56 BMACC56 Verilog Instantiation Template BMACC56 #( .init_a(28'h0), .init_b(28'h0), .init_sub(1'b0), .init_cin(1'b0), .init_mask_adda(1'b0), .init_dout(56'h0), .init_cout(1'h0), .rst_value_a(28'h0), .rst_value_b(28'h0), .rst_value_sub(1'b0), .rst_value_cin(1'b0), .rst_value_mask_adda(1'b0), .rst_value_dout(56'h0), .rst_value_cout(1'h0), .regce_priority_a(“regce”), .regce_priority_b(“regce”), .regce_priority_sub(“regce”), .regce_priority_cin(“regce”), .regce_priority_mask_adda(“regce”), .
Multipliers BMACC56 .ce_mask_adda(user_ce_mask_adda), .ce_dout(user_ce_dout), .rst_a(user_rst_a), .rst_b(user_rst_b), .rst_sub(user_rst_sub), .rst_cin(user_rst_cin), .rst_mask_adda(user_rst_mask_adda), .rst_dout(user_rst_dout), .cascade_in(user_cascade_in), .clk(user_clk), .dout(user_dout), .cout(user_cout), .cascade_out(user_cascade_out)); BMACC56 VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
Multipliers BMACC56 reg_addb => ‘0’; reg_mask_adda => ‘0’; reg_dout => ‘0’; reg_cout => ‘0’; sel_cascade_in => ‘0’; sel_cascade_out => ‘0’; sel_sub => “00”; sel_cin => “00”; mult_bypass => ‘0’; clock_edge => ‘0’) port map(a => user_a, b => user_b, sub => user_sub, cin => user_cin, mask_adda => user_mask_adda, ce_a => user_ce_a, ce_b => user_ce_b, ce_sub => user_ce_sub, ce_cin => user_ce_cin, ce_mask_adda => user_ce_mask_adda, ce_dout => user_ce_dout, rst_a => user_rst_a, rst_b => user_rst_b, rst_sub => us
Multipliers BMULT28X28 BMULT28X28 28 28 Signed Multiplier din0[27:0] BMULT28X28 dout[55:0] din1[27:0] Figure 7-3: Logic Symbol BMULT28X28 implements a signed 28 28 multiplier that multiplies two signed (two’s complement) 28‐bit inputs for produce a 56‐bit signed product. Table 7-6: Pin Description Name Type Description din0[27:0], din1[27:0] input Signed (two’s complement) 28-bit multiplier inputs. Bit 0 is the LSB. dout[55:0] output Signed (two’s complement) 56-bit product.
Chapter 8 – Special Functions ACX_DESERIALIZE (Speedster22iHP Only) 1:N Serial-to-Parallel Converter ACX_DESERIALIZE d q[output_width - 1 : 0] ck Figure 8-1: Logic Symbol ACX_DESERIALIZE implements an 1:N serial‐to‐parallel conversion of the data input, where N is specified by the output_width parameter. The parallel output stream, q, is output at N times slower than the frequency of clk.
Special Functions ACX_DESERIALIZE (Speedster22iHP Only) VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation ACX_DESERIALIZE_instance_name : ACX_DESERIALIZE generic map (output_width => 4) port map (q => user_q, d => user_d, clk => user_clk); Speedster Macro Cell Library www.achronix.
Special Functions ACX_SERIALIZE (Speedster22iHP Only) ACX_SERIALIZE (Speedster22iHP Only) N:1 Parallel-to-Serial Converter ACX_DESERIALIZE d[input_width - 1 : 0] q ck Figure 8-2: Logic Symbol ACX_SERIALIZE implements an N:1 parallel‐to‐serial conversion of the data input, where N is specified by the input_width parameter. The serial output stream, q, is output at N times faster than the frequency of clk.
Special Functions ACX_SERIALIZE (Speedster22iHP Only) library speedster22i; use speedster22i.components.all; ------------- DONE ACHRONIX LIBRARY ---------- Component Instantiation ACX_SERIALIZE_instance_name : ACX_SERIALIZE generic map (input_width => 4) port map (q => user_q, d => user_d, clk => user_clk); Speedster Macro Cell Library www.achronix.
Chapter 9 – PLL/DLL Clock Generators ACX_CLKGEN Phase-Locked Loop Clock Generator ACX_CLKGEN refclk fbclk clkout[3:0] pll_lock rstn core_clken[3:0] phase_inc[3:0] outphrstn ick_sbus_data[1:0] ick_sbus_req ick_dspll_sif_clk ick_dspll_sif_rstn ock_sbus_ack ock_sbus_data[1:0] Figure 9-1: ACX_CLKGEN Logic Symbol The reference clock, refclk, is divided by the reference clock divider (6-bit: 1 to 36) before it is sent to the Phase Frequency Detector (PFD).
PLL/DLL Clock Generators ACX_CLKGEN ACX_CLKGEN Pins Table 9-1: Ports Name Type Description refclk input Reference Clock. The reference clock, which is optionally divided by the Reference Divider, is fed into the Phase Frequency Detector. The input to the Phase Frequency Detector must be in the range of 30 MHz to 400 MHz. fbclk input Feedback Clock. The user may connect the Feedback Clock to one of the generated clkout[3:0] outputs so that the PLL may compensate for the delay of the clock network.
PLL/DLL Clock Generators ACX_CLKGEN Parameters Table 9-2: Parameters Parameter Description Defined Values Default Value 6’h01 - 6’h24 6’h1 clkdiv Reference Divider value. intfb Internal Feedback Enable. 0: Disable internal feedback. 1: Enables (internal) feedback divisor. 1’b0,1’b1 Mixed Feedback Mode. Not supported if intfb=0. 0: Pure internal feedback mode (if intfb = 1), Pure external feedback mode (if intfb = 0) 1: Mixed feedback mode (if intfb = 1).
PLL/DLL Clock Generators ACX_CLKGEN Parameter bypass2 Description Default Value 1’b0,1’b1 1’b0 1’b0,1’b1 1’b0 Clkout[2] Bypass. 0: clkout[2] driven by PLL output. 1: clkout[2] driven by refclk input. bypass3 Defined Values Clkout[3] Bypass. 0: clkout[3] driven by PLL output. 1: clkout[3] driven by refclk input. outdiv0 Clkout[0] Rotator / Output Divider Divisor. 6’h1-6’h3F 6’h4 outdiv1 Clkout[1] Rotator / Output Divider Divisor.
PLL/DLL Clock Generators ACX_CLKGEN Defined Values Default Value 1’b0,1’b1 1’b0 1’b0,1’b1 1’b0 1’b0,1’b1 1’b0 1’b0,1’b1 1’b1 1’b0,1’b1 1’b1 1’b0,1’b1 1’b1 1’b0,1’b1 1’b1 The output synthesizer divides the PLL output clock by 'high_cnt0 + low_cnt0'. The ratio of high_cnt0 to 'high_cnt0 + low_cnt0' determines the output duty cycle. 10’h000-10’h3FF 10’h0 The output synthesizer divides the PLL output clock by 'high_cnt0 + low_cnt0'.
PLL/DLL Clock Generators ACX_CLKGEN Description Defined Values Default Value The output synthesizer divides the PLL output clock by 'high_cnt2 + low_cnt2'. The ratio of high_cnt2 to 'high_cnt2 + low_cnt2' determines the output duty cycle. 10’h000-10’h3FF 10’h0 If set to 0, the output synthesizer is bypassed. Otherwise, the output synthesizer divides the PLL output clock by 'high_cnt2 + low_cnt2'. The ratio of high_cnt2 to 'high_cnt2 + low_cnt2' determines the output duty cycle.
PLL/DLL Clock Generators ACX_CLKGEN Figure 9-2: ACX_CLKGEN Block Diagram ACX_CLKGEN Phase Frequency Detector Reference Divider (M) refclk Voltage Controlled Oscillator Phase Rotator w/ Output Divider (N) Output Synthesizer (P) clkout[3] Phase Rotator w/ Output Divider (N) Output Synthesizer (P) clkout[2] Phase Rotator w/ Output Divider (N) Output Synthesizer (P) clkout[1] Phase Rotator w/ Output Divider (N) Output Synthesizer (P) clkout[0] fbclk 1 0 phaseinc_sat Feedback Divider (Q) rs
PLL/DLL Clock Generators ACX_CLKGEN However, output cycles other than 50% are not supported at this time. If (high_cnt + low_cnt) is an odd sum, then half_cycle must be 1 to ensure a 50% duty cycle. If enabled, when configured with a 50% duty cycle, the Output Synthesizer will act as a simple divider.
PLL/DLL Clock Generators ACX_CLKGEN Mixed Feedback Mode Mixed Feedback mode should only be used in the case that the output divider range is not enough. The VCO is divided by the output divider inside one of the phase rotators. The clkout output of the PLL, after it has been sent through the clock network, is fed back to the PLL for deskewing. The feedback clock is sent to the Feedback Divider before it is sent to the Phase Frequency Detector.
PLL/DLL Clock Generators ACX_CLKGEN Figure 9-3: Serial Control Bus Read Operation ick_dspll_sif_clk ick_sbus_req ick_sbus_data[1:0] {A0,1’b0} {A2,A1} {A4,A3} {A16,A15} ock_sbus_ack ock_sbus_data[1:0] {D1,D0} {D3,D2} {D29,D28} {D31,D30} Figure 9-4: Serial Control Bus Write Operation ick_dspll_sif_clk ick_sbus_req ick_sbus_data[1:0] {A0,1’b1} {A2,A1} {A16,A15} {D1,D0} {D3,D2} {D31,D30} ock_sbus_ack Control Status Registers (CSR) Register Description Table 9-4: Control Status Registers (CSR) De
PLL/DLL Clock Generators CSR NAME CSR_ADDR_SYNTHOUT1 CSR_ADDR_SYNTHOUT2 CSR_ADDR_SYNTHOUT3 CSR_ADDR_USER_RESERVE_05 CSR_ADDR_USER_RESERVE_06 Speedster Macro Cell Library ACX_CLKGEN Addr.
PLL/DLL Clock Generators CSR NAME CSR_ADDR_SYNTHOUT_BYPAS S_RST CSR_ADDR_SYNTHMDIV CSR_ADDR_SYNTHREFDIV CSR_ADDR_SYNTHPROPGAIN Speedster Macro Cell Library ACX_CLKGEN Addr.
PLL/DLL Clock Generators CSR NAME ACX_CLKGEN Addr.
PLL/DLL Clock Generators CSR NAME CSR_ADDR_DFTADDR CSR_ADDR_PLL_CTL1 CSR_ADDR_PLL_CTL2 CSR_ADDR_PLL_CTL3 CSR_ADDR_PLL_CTL4 Speedster Macro Cell Library ACX_CLKGEN Addr. Bit 8’h10 8’h11 8’h12 8’h13 8’h14 Type Initial Value Description 0 in/out Reserved Reserved 1 in/out Reserved Reserved 2 in/out Reserved Reserved 3 in/out Reserved Reserved 4 in/out Reserved Not Used. 5 in/out Reserved Not Used. 6 in/out Reserved Not Used. 7 in/out Reserved Not Used.
PLL/DLL Clock Generators CSR NAME CSR_ADDR_LDO_CTL CSR_ADDR_BGR_CTL1 CSR_ADDR_BGR_CTL2 CSR_ADDR_ADC_CTL1 CSR_ADDR_ADC_CTL2 Speedster Macro Cell Library ACX_CLKGEN Addr.
PLL/DLL Clock Generators ACX_CLKGEN CSR NAME CSR_ADDR_ADC_DATA1 CSR_ADDR_ADC_DATA2 CSR_ADDR_USER_CONTROL Addr.
PLL/DLL Clock Generators ACX_CLKGEN .low_cnt0 .half_cycle0 .clken_out0 (10'h0), (1'b0), (1'b1), .bypass1 .outdiv1 .en_phase1 .static_phase1 .dyn_phase1 .byp_clkdiv1 .high_cnt1 .low_cnt1 .half_cycle1 .clken_out1 (1'b0), (6'h4), (1'b1), (3'h0), (1'b0), (1'b1), (10'h0), (10'h0), (1'b0), (1'b0), .bypass2 .outdiv2 .en_phase2 .static_phase2 .dyn_phase2 .byp_clkdiv2 .high_cnt2 .low_cnt2 .half_cycle2 .clken_out2 (1'b0), (6'h4), (1'b1), (3'h0), (1'b0), (1'b1), (10'h0), (10'h0), (1'b0), (1'b0), .
PLL/DLL Clock Generators ACX_CLKGEN VHDL Instantiation Template ------------- ACHRONIX LIBRARY -----------library speedster22i; use speedster22i.components.
PLL/DLL Clock Generators ACX_CLKGEN dyn_phase3 => "0", byp_clkdiv3 => "1", high_cnt3 => "0000000000", low_cnt3 => "0000000000", half_cycle3 => "0", clken_out3 => "0") port map ( refclk => user_refclk, fbclk => user_fbclk, rstn => user_rstn, outphrstn => user_outphrstn, core_clken => user_core_clken, phase_inc => user_phase_inc, clkout => user_clkout, ick_dspll_sif_clk => user_ick_dspll_sif_clk, ick_dspll_sif_rstn => user_ick_dspll_sif_rstn, ick_sbus_data => user_ick_sbus_data, ick_sbus_req => user_ick_sbu
Revision History The following table lists the revision history of this document. Version 1.0 Speedster Macro Cell Library Revision Initial released version. 1.1 • 2/2/2012 ACE 4.1 Release. 1.2 • 3/31/2012 ACE 4.2 Release 1.3 • 5/4/2012 ACE 4.2 Release 1.4 • 10/25/2012 ACE 5.0 Release 1.5 • 3/29/2013 ACE 5.1 Release 1.6 • 8/4/2014 ACE 5.3 Release 1.7 • 10/2 4/2014 Updated Registers section www.achronix.
