User Macro Guide

Table 1-7: Ports
Name Type Description
pad Bidirectional device pad.
din
Positive-edge based data input. I
f parameter txregmode=”reg”, data is
clocked into the din register upon the rising edge of the clk input, and is
driven to the pad if the oe input was high before the rising edge of the clk
input. If parameter txregmode=”nonreg”, din is driven to the pad when the
output is enabled (oe=1).
dout
Positive-edge based data output. I
f parameter rxregmode=”reg”, data is
clocked from the pad to dout on the rising edge of clk. If parameter rxreg-
mode=”nonreg”, the input register is b
ypassed and the pad is driven onto
output dout.
oe
Output Enable.
The output enable register transitions upon the rising edge
of the oeclk clock. A low value on the rstn input performs an asynchronous
clear to disable the output when the output enable is set to registered mode
by setting the oeregmode parameter to “reg”. A high value on oe enables the
output pad upon the next rising edge of the clock when the Output Enable
register is enabled. A low value on oe disables the pad upon the next rising
edge of the clock and places the pad in high impedance mode when the Out-
put Enable register is enabled. If the output ena
ble register is bypassed by
setting the txregmode parameter to “nonreg”, driving oe high immediately
enables the pad.
txdata_en
Output Register Clock Enable. A
high value on txdata_en enables the
Output Register to clock the din input to the output at the next rising edge
of the txclk. A low value on txdata_en allows the Output Register to retain
its current value.
rxdata_en
Input Register Clock Enable.
A high value on rxdata_en enables the
Input Register to clock the value on pad into the Input Register at the next
rising edge of the rxclk. A low value on rxdata_en allows the Input Regis-
ter to retain its current value.
txrstn
Output Register Asynchronous Reset. A
low value on txrstn performs an
asynchronous initialization of the Output Register. The value initialized
into the Output Register is determined by the value of the rstvalue param-
eter.
rxrstn
Input Register Asynchronous Reset. A low val
ue on rxrstn performs an
asynchronous initialization of the Input Register. The value initialized into
the Input Register is determined by the value of the rstvalue parameter.
oerstn
Output Enable Register Asynchr
onous Reset. A low value on oerstn per-
forms an asynchronous initialization of the Output Ena
ble Register and ini-
tializes it to a low value to put the
output in a high-impedance mode.
srstn
Synchronous Reset. A
low value on srstn performs a synchronous initial-
ization of the input register and output r
egister if the rstmode parameter is
set to "sync". Setting the rstmode parameter to "async" disables the syn-
chronous reset.
txclk Output Register Clock input for transmit side.
rxclk Input Register Clock input for receive side.
oeclk Output Enable Regist
er Clock input.
I/O Cells IOPAD_D
Speedster Macro Cell Library
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