Acorn Archimedes 500 series Acorn R200 series Service Manual
Copyright © Acorn Computers Limited 1991 Neither the whole nor any part of the information contained in, nor the product described in this manual may be adapted or reproduced in any material form except with the prior written approval of Acorn Computers Limited. The products described in this manual, and products for use with it are subject to continuous development and improvement.
Service Manual Contents About this manual vi Part 1 - System description 1-1 Introduction General System timing 1-1 1-1 1-2 The I/O system The sound system The keyboard and mouse Floppy disc drive Power supply Hard disc drive Main PCB Links Plugs 1-3 1-9 1-10 1-14 1-15 1-15 1-17 1-18 Sockets Internal expansion 1-18 1-19 Part 2 - Interface cards 2-1 Ethernet interface Overview Ethernet I expansion card Ethernet II expansion card SCSI interface 2-1 2-1 2-1 2-13 2-18 Part 3 - Disassembly and ass
Service Manual Part 4 - Fault diagnosis 4-1 Test equipment required Checking a 'dead' computer Functional testing General test procedure Preparing to run the tests Creating a CMOS test data file Completing the tests Main PCB functional test suite Individual tests 4-1 4-2 4-4 4-4 4-5 4-6 4-6 4-7 4-15 Part 5 - Main PCB fault diagnosis 5-1 Test equipment you will need 5-1 Integral test software overview Power-on self-test (POST) Using the test link Using the display adapter Using the external diagnosti
Service Manual Appendix A - Mouse test jig template A-1 Appendix B - Ethernet test feedback leads B-1 Appendix C - Serial port Ioopback plug C-1 Appendix D - Earth continuity testing D-1 Appendix E - DC insulation testing - class 1 E-1 Drawings • • • • • • • • • • Contents Final assembly drawings SCSI interface card circuit diagram Ethernet I expansion card circuit diagram Ethernet II expansion card circuit diagram Main PCB circuit diagram Main PCB assembly drawing 4MB RAM upgrade circuit diagr
Service Manual About this manual This manual is intended as a service manual for the following models: • Archimedes 540 • Acorn R260 • Acorn R225 Throughout the remainder of this manual, the generic term workstation will be used to refer to the above, unless a reference to a specific model is required. This manual supplements the basic information given on system hardware in the installation Guide and Technical Reference Manual (available for separate purchase).
Service Manual Part 1 - System description Introduction General The workstation is built around the ARM chip set, comprising the Acorn"RISC Machine (ARM) itself, the Memory Controller (MEMC), Video Controller (VIDC) and Input Output Controller (IOC). The ARM3 CPU is a pipelined, 32-bit reduced instruction set microprocessor which accepts instructions and manipulates data via a high speed 32bit data bus and 26-bit address bus, giving a 64 MB uniform address space.
Service Manual MEMC acts as the interface between the ARM, VIDC, IOC, ROM (Read-Only Memory) and DRAM (Dynamic RAM) devices, providing all the critical system timing signals, including processor clocks. Up to 4 MB of DRAM is connected to the 'Master' MEMC which provides all signals and refresh operations. A Logical to Physical Translator maps the Physical Memory into a 32 MB Logical address space ( with three levels of protection) allowing Virtual Memory and Multi-Tasking operations to be implemented.
Service Manual The I/O system System architecture The I/O system is controlled by IOC, MEMC and two PALs. The I/O bus supports all the internal peripherals and the expansion cards. The I/O system (which includes expansion card devices) consists of a 16-bit data bus (BD[0:15]), a buffered address bus (LA[2:21]), and various control and timing signals. The I/O data bus is independent of the main 32bit system data bus, being separated from it by bidirectional latches and buffers.
Service Manual Data bus mapping Expansion card identification The mapping of the BD[0:15] bus onto the D[0:31] bus is as follows: During a WRITE (ie ARM to peripheral) D[16:31] is mapped toBD[0:15]. I/O address memory mapping The I/O data bus is 16 bits wide. Bytewide accesses are used for 8-bit peripherals. The I/O data bus (BD[0:15]) connects to the main system data bus (D[0:31]) via a set of bidirectional data latches.
Service Manual Internal register memory map Address Read Write 3200000H 3200004H Control Control Serial Rx Data 3200008H - 320000CH - - 3200010H IRQ status A - 3200014H IRQ request A IRQ clear 3200018H IRQ mask A IRQ mask A 320001CH - - 3200020H IRO status B - 3200024H IRQ request B - 3200028H IRQ mask B IRQ mask B 320002CH - - 3200030H FIQ status - 3200034H FIQ request - 3200038H FIQ mask FIQ mask 320003CH - - 3200040H T0 count Low T0 latch Low 3200044H T
Service Manual I/O programming details External latch B External latch A External Latch B is a write only register shared between several users who must maintain a consistent RAM copy. Updates must be made with IRQ disabled. External latch A is a write only latch used to control parts of the floppy disc sub-system: Bit 0-3 4 Bit Name Function Floppy disc sel. These bits select the floppy disc drive 0 through 3 when written LOW. Only one bit should be LOW at any one time.
Service Manual IRQ status A Interrupts The I/O system generates two independent interrupt requests, IRO and FIQ. Interrupt requests can be caused by events internal to IOC or by external events on the interrupt or control port input pins. The interrupts are controlled by four types of register: • status • mask • request • clear The status registers reflect the current state of the various interrupt sources. The mask registers determine which sources may generate an interrupt.
Service Manual Control port IRQ status B Bit Name 0 Podule FIQ req Function This bit indicates that a Podule FIQ request has been received. It should usually be masked OFF. The control register allows the external control pins C[0:5] to be read and written and the status of the PACK and VFLY inputs to be inspected. The C[0:5] bits manipulate the C[0:5] I/O port. When read, they reflect the current state of these pins. When written LOW the output pin is driven LOW.
Service Manual The sound system MEMC sound system hardware The sound system is based on the VIDC stereo sound hardware. External analogue anti-alias filters are used which are optimised for a 20 kHz sample rate. The high quality sound output is available from a 3.5mm stereo jack socket at the rear of the machine which will directly drive personal stereo headphones or alternatively an amplifier and speakers. One internal speaker is fitted, to provide mono audio.
Service Manual The keyboard and mouse The keyboard assembly comprises a membrane keyswitch panel connected to an adaptor PCB, which serialises the keyboard and mouse data; connection to the ARM is made via a serial link to the IOC. The ARM reads and writes to the KART registers in the IOC. The protocol is essentially half duplex, so in normal operation the keyboard will not send a second byte until it has received an Ack.
Service Manual the LED status. After the reset sequence, key scanning will only be enabled if a scan enable acknowledged ( SACK or SMAK) was received from the ARM. Data transmission When enabled for scanning, the keyboard controller informs the ARM of any new key down or new key up by sending a two byte code incorporating the key row and column addresses. The first byte gives the row and is acknowledged by a byte acknowledge (BACK) code from the ARM.
Service Manual Similarly, a key release is ignored while scanning is off. Commands may be received at any time. Therefore, commands can be interleaved with acknowledge replies from the ARM, eg keyboard sends KDDA (first byte), keyboard receives command, keyboard receives BACK, keyboard sends KDDA (second byte), keyboard receives command, keyboard receives SMACK. If the HRST command is received the keyboard immediately enters the restart sequence. The LEDS and PRST commands may be acted on immediately.
Service Manual Base Keyswitch mapping (UK 103 key keyboard) name Row code Col. code 1.5 1 Tab Q 2 2 6 7 1 W 2 8 1 E 2 9 1 R 2 A Key size Key Notes Key Key size name Row code Col. code Notes 1 1 Esc F1 0 0 0 1 1 2 1 F2 0 2 2 1 F3 0 3 2 1 F4 0 4 2 1 T 2 B 1 F5 0 5 2 1 Y 2 C 1 F6 0 6 2 1 U 2 D 1 F7 0 7 2 1 I 2 E 1 F8 0 8 2 1 0 2 F 1 F9 0 9 2 1 P 3 0 2 1 [{ 3 1 1 ]} 3 2 1.
Service Manual Floppy disc drive Keyswitch mapping (cont.) Key Name Row code Col. code Notes Size 2.25 1 1 1 1 1 1 1 1 1 1 2.75 1 1 1 1 shift Z X C V B N M ,< .> / shift crsrUp 1 2 3 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 C E F 0 1 2 3 4 5 6 7 8 9 A B C 1,3 1.5 1.5 7.0 1.5 1.5 1 1 1 2.0 1 Caps Alt Space Alt Ctrl crsrLt crsrDn crsrRt 0 . Enter 5 5 5 6 6 6 6 6 6 6 6 D E F 0 1 2 3 4 5 6 7 1,4 1,3 Key 2.
Service Manual Power supply Hard disc drive Performance characteristics Performance Min Nom Max Units Input voltage (47-53 Hz) 198 220/ 240 264 Vac *Input voltage (57-63 Hz) 98 110 132 Vac Output voltage VO1 4.9 5 5.1 Vdc Output current 101 1.5 - 12.2 Amps dc 50 mV pk-pk Output ripple and noise VO1 BW 0-20MHz Overshoot VO1 0.1 Vdc 7.0 Vdc 14.5 Amps dc 1.0 Sec 11.4 12 12.6 Vdc 0 3.2 Amps dc Output ripple and noise V02 100 mV pk-pk Overshoot VO2 0.
Service Manual 1-16 Issue 2, June 1991 Part 1 - System description
Service Manual Main PCB Links Part 1 - System description Issue 2, June 1991 1-17
Service Manual Plugs 1-18 Sockets Issue 2, June 1991 Part 1 - System description
Service Manual Internal expansion Sockets (cont.) Skt Fitted SK11 Yes SK12 Yes SK13 Yes Interface Function/Specification 6-way mini-DIN socket providing the connection point for the keyboard. If required, a standard Archimedes keyboard may be plugged into this socket. High resolution mono video output. Provides a 0.7V mono video signal (into 75 Ohm) at a dot rate of 96MHz. This requires a High resolution monitor to be connected. High resolution mono vertical sync.
Service Manual 1-20 Issue 2, June 1991 Part 1 - System description
Service Manual Part 2 - Interface cards Ethernet interface Ethernet I expansion card Where an Ethernet interface is fitted, it is provided by one of two different types of Ethernet expansion card, identified as Ethernet I and Ethernet II. Both cards can support either a Thick' or 'thin' (Cheapernet) Ethernet interface. Figure 2-1: Ethernet I expansion card block diagram is a block diagram of the Ethernet/Cheapernet podule.
Service Manual The Intel chip set As the Xerox and IEEE standards have become widely accepted, a number of systems companies have produced VLSI devices that considerably reduce the design effort required to implement a connection. The most notable of these are by Advanced Micro Devices (AMD) and Intel. The Intel chip set comprising the 82586 local area network coprocessor, the 82501 Ethernet serial interface, and the 82502 Ethernet transceiver chip has been used in this design.
Service Manual The LANCE The 82586 LANCE is a 'scatter-gather' DMA controller type device and is designed to interface to 80186 type processors using a HOLD/HOLDA protocol to resolve arbitration for access to shared memory. The ARM podule bus cannot easily support a HOLD/HOLDA type interface. This is because the ARM is a dynamic device and cannot be stopped for the required time. (This can be longer than 10µs during the interframe/interpacket spacing time.
Service Manual and the ARM has to correct the count. Error counts this high indicate a major problem that will require correction so should be a rare event. The memory bus of the LANCE is operated in 'minimum mode' as the timing parameters for LANCE outputs in this mode are subject to less spread between devices. The pull-up resistors on WR*, RD*, and BHE are required to prevent RAM cycles when the LANCE is inactive.
Service Manual Table 2-2: Podule identity PROM Part 2 - Interface cards Issue 2, June 1991 2-5
Service Manual The state machine and operation The state machine has four states; IDLE, SA1, SA2, and SA3 and is clocked from state to state on the falling edge of CLK8, the 8 MHz podule bus clock. See Figure 2-2: State diagram. The idle state The state machine enters this state on power-up, hard reset (RST* low), or from the SA3 state. In this state the bus buffers on the ARM side of the dual-ported RAM are disabled and those on the LANCE side enabled.
Service Manual Figure 2-3: Typical podule bus cycle Part 2 - Interface cards Issue 2, June 1991 2-7
Service Manual Figure 2-4: Access collision cases PS* while LANCE is in T1 PS* while the LANCE is in T1 The LANCE samples READY deasserted at the end of T2 (SA2), and then again at the end of TW1 (SA3), so in this case two wait states are inserted. Figure 2-5: Access collision cases PS* while LANCE is in T2 PS* while the LANCE is in T2 The LANCE samples READY deasserted at the end of T2 (SA1), TW1 (SA2), TW2 (SA3), so the maximum of three wait states are inserted.
Service Manual Figure 2-6: Access collision cases PS* while LANCE is in T3 PS* while the LANCE is in T3 In this case READY is still active when the LANCE samples it at the end of T3 ( idle). This is the last time that the LANCE does this for the current cycle so the LANCE cycle completes before the podule bus cycle starts. Note that the LANCE is not active on the RAM bus during T4.
Service Manual PS* while the LANCE is idle If the LANCE remains idle while the podule bus cycle occurs then there is no collision and the LANCE ignores the READY signal. This case is not illustrated. A read from the podule ID PROM or write to the control or page register is similar to a RAM cycle. To simplify the bus design the LANCE is removed from the RAM buses during cycles to these devices.
Service Manual Figure 2-9: State diagram for INTO/PIRQ* Figure 2-10: State diagram for INTEN* Part 2 - Interface cards Issue 2, June 1991 2-11
Service Manual Links The Ethernet I PCB should be viewed from the component side with the 96 way podule bus connector on the left and the rear panel on the right. When viewed like this, west is to the left, east the right, north the top and south the bottom. LK1 and LK2 select the RAM size If 32 KB devices are fitted (normally) the links should both be south. 8 KB devices will not normally be fitted but in this case LK1 and LK2 should be north. LK3 to LK8 select Ethernet or Cheapernet.
Service Manual Ethernet II expansion card The IEEE 803.2 standard supports two different versions for the media: • 10BASE5 (commonly known as Ethernet) • 10BASE2 (thin-wire Ethernet, or 'Cheapernet'). These can be used-separately, or together in a hybrid form. Both versions have similar electrical specifications and can be implemented using the same transceiver chip. Thin-wire Ethernet is the lower cost version and is userinstallable.
Service Manual interrupt location, the Ethernet ID of the particular board (each PROM is programmed with a different number) and required driver code to run under RISC OS. It is page addressed by writing to 'mode' latch. System reset sets to page zero. 3 Data Buffer: Static RAM memory. Memory access is completely controlled by the NIC controller which performs the memory management. Data is transferred between the controller and SRAM using local DMA, and between the SRAM and the PORT by remote DMA.
Service Manual Circuit component details transferred automatically between the Port and Network via the NIC and SRAM. Decode and cycle access control The Ethernet II expansion card has hardware in both podule space and Module space. The podule section consists of the ID/RISC OS driver EPROM, the interrupt status register and the EPROM page register.
Service Manual Local Buffer Memory The buffer memory consists of two 8k x 8 (up to 512k x 8 for SRAM source flexibility) static RAMs which give a 16 bit data transfer across the podule interface, hence maximizing the podule bandwidth. The data buffer is completely controlled by the NIC controller, which performs all the memory management in a ring buffer format. Pointers to the memory are updated as required ( but can be accessed via the NIC registers if necessary).
Service Manual Bibliography Summary The Ethernet II expansion card hardware design tries to be as transparent, in terms of data transfer, as possible. Where design requirements have allowed, flexibility has been given to the way the software can use this hardware platform, at the same time trying to maintain minimum system overhead.
Service Manual SCSI interface Circuit description of the SCSI expansion card (Issue 2+) Overview Maximum performance is achieved from the Acorn expansion bus by the use of the STM (STore Multiple) and LDM (LoaD Multiple) ARM assembler instructions to transfer data to and from a peripheral device. These instructions, coupled with the full use of the 16 bit I/O data bus, will provide a maximum data transfer rate of 8 MB per second.
Service Manual The final section of the podule hardware is the interrupt control logic. There are two sources of interrupts within the SEC, the DMAC and the SBIC. The DMAC will issue a terminal count (TC) pulse at the end of a data transfer which will be latched by the ISR, and may be subsequently read at any time by the ARM processor. SBIC interrupts are latched within the SBIC, but can be monitored in the ISR. DMAC interrupts remain latched until the Clear Interrupt (CLRINT) address is written to.
Service Manual HCT273), which are directly connected to the EPROM, but isolated from the SRAMs by IC3 (HCT541). The EPROM (IC5) and the ISR (IC15, PAL 0273,215) also have an 8 bit data bus buffer (IC2 HC245) separate from that used for the SRAMs, DMAC and SBIC. Again, this allows ARM access independent of DMA activity. IC4 ( HC245) and 106 (HC245) provide 16 bits of data bus buffering for the SRAMs (IC13 and IC11), as well as the DMAC and SBIC.
Service Manual Figure 2-13 Figure 2-14 Part 2 - Interface cards Issue 2, June 1991 2-21
Service Manual Figure 2-15 2-22 Issue 2, June 1991 Part 2 - Interface cards
Service Manual Glossary of terms for PAL signal names SCSI SBIC DMAC SRAM Small computer systems interface SCSI bus interface controller Direct memory access controller Static random access memory PCLK8M CLRINT INTE TC INTRQ ARMA MS URST RST ABE IRST IRQ DINT FIQ SINT SRST PIRQ PRE PWE LA12 LA13 PS DACK A0 A23 EPRM SRLO SRHI PAGE INTRD AEN IORQ HLDRQ STAGE PNRW BL LBL LIOGT REL EXTRW HLDAK IOGT RA7 8MHz clock Clear interrupt Interrupt enable Terminal count Interrupt request ARM processor access Module se
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Service Manual Part 3 - Disassembly and assembly DANGER: BEFORE REMOVING THE TOP COVER, ENSURE THAT THE COMPUTER SYSTEM HAS BEEN SWITCHED OFF AND THE MAINS PLUG REMOVED FROM THE SUPPLY. REMOVING THE TOP COVER GIVES ACCESS TO THE POWER SUPPLY. ALTHOUGH THE POWER SUPPLY IS DESIGNED TO COMPLY WITH BS7002/EN60950 CLASS 1, YOU MUST STILL TAKE CARE TO ENSURE THAT NO METAL OBJECTS FALL (OR ARE PUT) INTO THE POWER SUPPLY UNIT THROUGH THE VENTILATION HOLES.
Service Manual Removing cables Note: On an R225, ignore references to cables attached to hard or floppy drives 1 Disconnect the cables from the following plugs on the main board: • PL4 (floppy drive controller cable) • PL2 (floppy drive power cable) • PL5 (PSU power cable) 2 Remove the hard disc power cable from the rear of the hard disc drive. 3 Disconnect the twisted pair leads for the speaker and the green power-on LED by removing the connectors from LK13 and LK14 on the main board.
Service Manual Note 2: The PSU is a service replacement only item. DANGER: WHEN REFITTING OR FITTING A REPLACEMENT ASSEMBLY, CHECKS SHOULD BE MADE FOR EARTH CONTINUITY AS DESCRIBED-IN Appendix D - Earth continuity testing. Assembly Keyboard assembly is generally in reverse order, with the following notes: Slot the PCB support tray under the two fixing screws at the end furthest from the keyboard cable, then insert the remaining screws.
Service Manual 3-4 Issue 2, June 1991 Part 3 - Disassembly and assembly
Service Manual Part 4 - Fault diagnosis This chapter is a guide to the diagnosis and repair of basic faults in the Archimedes 500 series and R200 series computer systems. Additional test equipment required when testing expansion cards It consists of algorithms to enable you to trace and remedy faults in a 'dead' computer, followed by instructions for running the Archimedes functional test software, which is designed to isolate faults in a computer which is working.
Service Manual Checking a 'dead' computer This section covers the initial tests that you should perform on an apparently 'dead' computer to discover which module or upgrade is faulty. If the computer is partially working (ie any faults occur after a successful power-up) go straight to the section entitled Functional testing on page 4-4. Follow the instructions shown in the flow chart opposite. Notes: 1 You may need to reconfigure the CMOS RAM to its original (factory) default.
Service Manual Part 4 - Fault diagnosis Issue 2, June 1991 4-3
Service Manual Functional testing Notes: The following information gives details of how to isolate faults to individual modules, using the dealer test disc ( 0286,832) on machines which are running, but exhibiting faults. The tests included on the disc can be divided into two groups as follows: 2 You must switch off the equipment and disconnect from the mains supply BEFORE removing any other connections. • Test suite — includes everything needed for testing a standard configuration machine.
Service Manual Creating a test SCSI hard disc To avoid overwriting the customer's hard disc during testing, prepare a test hard disc as follows: Equipment required • SCSI Hard disc to be initialised(UUT) • A500 series test station (do not use a customer's computer for this test) • 3.5" Winchester initialiser test disc (0286,822) (write protected) • Standard RGB colour monitor (Analogue RGB) and cable.
Service Manual You need to save the contents of the CMOS RAM before any of the tests you run, and restore them when the last test is over: 1 Insert the dealer test disc (0286,832) into the floppy disc drive. 2 Hold down the Shift key and switch the computer on ( do NOT touch the Delete key). Keep the Shift key held down while the computer powers up. The following menu will be displayed: Menu Vx.
Service Manual 9 Switch off the power to the rest of the equipment. 10 Replace the test hard disc if fitted, with the original. 11 Check the refitted hard disc starts up properly – power up the equipment, click the mouse over the hard disc icon and ensure a directory viewer appears. 12 Shutdown the unit under test: • press F12 and type SHUTDOWN (then press Return) Or • select Shutdown from the task manager menu. 13 Switch off the power to the computer (at the mains switch on the rear of the machine).
Service Manual 3 Select the A500 option from the next menu which will configure the CMOS RAM for the selected computer. If only one option exists in the A500 series then the software will automatically select that option. If there is more than one option then a second menu will be displayed. Select the required option (eg A54 0 Dealer Acceptance Test). If the test type is not found in the test data file then a test type menu will be displayed. 4 A list of settings will then appear on the screen.
Service Manual PASSED PASSED PASSED PASSED PASSED PASSED PASSED PASSED PASSED Press F5 if correct, or F8 if not correct, to continue. You cannot press a function key until at least one cycle of each sound channel is complete. ST506 int. correct setup ST506 ext. correct setup FDC correct setup Serial correct setup Ethernet I correct setup Ethernet II correct setup SCSI Podule correct setup ROM Podule correct setup UPM correct setup Action if test falls: If no sound, check speaker connections.
Service Manual Check the following: • the 16 shades displayed • the mid-coloured border • the quality of the 'grey scale' display • the integrity of each test card. Press F5 if the display is correct, or F8 if not correct, to continue. These are subjective tests — note any failures. If the test fails due to the colours being incorrect or missing, proceed as follows: With a full white screen, VIDC IC 54 pins 39,40 and 41 should all have the same signal on them.
Service Manual External port tests You should be familiar with the correct print-out pattern before running this test. It should resemble Figure 4-3: Printer test output. While each test is being run the word Running will appear next to the test and-then, when the test is complete, the pass/fail message will overwrite it. The Printer test sends a test pattern to the printer. The pattern comprises a repeated series of stepped lines, each representing bits 0 to 7.
Service Manual Action if printer test fails • Check that the configuration settings for PRINTER and IGNORE are correct. • Check that the correct type of printer is called in the test data file, or check your notes when running the configuration program earlier in the test. • Check that the printer is on line and that the printer lead is connected correctly and functions correctly. • If the fault still persists then either change the main PCB, or see Part 5 - Main PCB fault diagnosis.
Service Manual Break and Escape key stuck sub-test If the Break or Escape keys are stuck down, the following message will be displayed on to the screen: THE ESCAPE OR BREAK KEYS ARE STUCK DOWN. REPLACE THE KEYBOARD The keyboard is faulty and should be rejected. If everything is normal and no keys are stuck then nothing is displayed on the screen and the program passes straight on to the next sub-test automatically. Reset button sub-test During the tests you will be asked to press the reset button.
Service Manual SCSI card test WARNING: This test will write to the SCSI hard disc. You should fit a test hard disc, or alternatively ensure that the customer is aware that their hard disc will be overwritten, and has given their consent before you start. The screen will clear and the following will be displayed SCSI PODULE Vx.
Service Manual ROM expansion card test Individual tests You can choose which tests you run from this section — they are not all run automatically in sequence. They are for testing an individual module or expansion card. So you have two options: • You can run any one of the tests described in the section entitled Main PCB functional test suite on page 4-7 by itself. See that section for a description of each module test.
Service Manual I/O expansion card test & Midi upgrade test The I/O expansion card test should be carried out whenever you install, repair or replace an I/O expansion card. The MIDI Upgrade test should be carried out whenever you install, repair or replace the MIDI Upgrade for the I/O expansion card. Note: These instructions assume that the I/O expansion card, the MIDI upgrade to the expansion card (if fitted) and the backplane have already been correctly installed.
Service Manual • one end of the Econet cable marked IN to the IN socket of the (uppermost) MIDI expansion card under test • the other end of this cable to the OUT1 socket of the (lower) known good MIDI expansion card • one end of the Econet cable marked 0/P to the IN socket of the (lower) known good MIDI expansion card • monitor to the mains supply (don't switch on yet) • computer to the mains supply (don't switch on yet). Note: At this stage the cable marked 0/P is only connected at one end.
Service Manual 2 Follow the instructions in the section entitled Preparing to run the individual expansion card tests on page 415. 3 Select the Ethernet I option. The test program is then loaded and executed. This test is only a partial test of the Ethernet card. The partial test tests the RAM, ROM and the transmit and receive circuitry when in loopback mode. When the test has finished, a board passed/failed message is produced.
Service Manual Part 5 - Main PCB fault diagnosis This chapter deals with fault diagnosis and repair of the main PCB at component level. The larger part of this chapter describes how to use the integral test software which is incorporated in the computer's ROMs, and includes details of the power-on self-test (POST), the fault display and the diagnostic interface. The remainder of the chapter gives details of how to repair a 'dead' computer (see the section entitled Repairing a 'dead' computer on page 5-23).
Service Manual 4 The screen colour reverts to purple and a test is performed for an ARM 3 processor. This test relies on good RAM, and will not be performed if a failure has already been detected. The following is a normal POST sequence: 1 The screen colour is first set to purple to indicate testing has started. The first part of the test: • • • performs a brief ROM and RAM test initialises the 10 controller initialises the Video controller.
Service Manual Thus a ROM failure (fault code 00000219 on an ARM 3 machine) will be displayed as: short short short short short short short short short short short short short short short short short short short short short short long short short short short long long short short long 0 0 0 0 0 2 1 9 The external test connector is the 6 pin link LK4 on the main PCB. It is situated near the four RAM upgrade sockets, as shown in Fig 5-2: Link positions on main PCB.
Service Manual Cycling reset You can find certain faults (such as address, data bus, or ROM faults) more easily by constantly cycling the reset line to the processor. This causes it to execute the first few instructions in the ROM repetitively. One way to do this is described in the section entitled Using the external diagnostic interface on page 5-9. However, you can instead use a fixed-rate oscillator that is built into the reset circuitry.
Service Manual reserved for data used to force the CRC of individual ROMs to be zero. This checksum should always total zero - if it doesn't, the message ROM bad xxxxxxxx (where xxxxxxxx is the calculated checksum in hexadecimal) is displayed. If a faulty checksum is detected, an additional test is performed to search for a possible ROM address line fault. This compares the words at the start of the ROM (&3800000) with data at a series of walking-one addresses (&3804000, &3808000, &3810000 etc).
Service Manual Note that the memory sizing algorithm uses address aliasing to determine the MEMC page size to be used. This may cause address line faults to result in an incorrect memory size detection rather than an address line error. The ARM memory interface is capable of both word and byte accesses to memory.
Service Manual These values will vary between machine types, and the bus cycle speed will improve when MEMC1 a is fitted. Note that ARM3 uses an additional clock for cached and internal operations which is not enabled when this test is performed. Large memory test The earlier memory tests performed brief checks on the memory control and data lines to ensure that the memory components were present and to assist in finding short or open circuits in the interconnections.
Service Manual CAM map xxx.yyyy The identifier at physical page xxx was not equal to that at logical page yyyy when they should be mapped together. CAM pmk xxx.yyyy The data found at logical page yyyy was the same as that at physical page xxx, but was not the expected value (ie the data had become corrupt) CAM als xxx.yyyy Physical page xxx was mapped at logical page yyyy as well as in it's proper place. CAM abo xxx.
Service Manual 000000 other Timers failed to get to TO done, T1 not done. Either indicate 10C cannot time properly Number of wait loops expired before failure. Since in this test the clock signals for IOC and VIDC are both derived from the same clock (see Fig 1-2: System timing on page 1-2) errors in the speed of this clock will result in the ratio remaining correct. A fault will not be indicated, but the measured processor speed may be abnormal.
Service Manual You can select the standard POST sequence: in fact, the display interface is hard-wired to generate this command then passively display the resulting text output. It is therefore also possible to display the POST results on the host's display. Note: if you attempt to access logical memory without first setting up MEMC, the target will trap with an exception error, jump to a vector which cannot be set up, and crash.
Service Manual *PMemoryA Display and alter target system memory Syntax *PMemoryA [-B] [] *PMemoryA [-BR] Parameters B Alter memory addressed as bytes R Perform the write operation repetitively Use *PMemoryA displays and modifies the contents of the target system memory, either interactively or using the new value given. This may also be used to program peripheral devices or initialise MEMO.
Service Manual *PGo *PReset Execute code on the target machine Syntax *PGo *PGo -V Perform a hardware reset on the target machine Syntax *PReset *PReset nn *Preset -P Parameters Address to begin execution Index into ROM vector table The following vectors are currently defined: 0 Restart the test code at the beginning 1 Restart test code, ignoring test adapter 2 Restart test code, simulating power-on reset 3 Restart test code, expecting display ada
Service Manual *PAddex *PDatex Exercise a specified memory location Syntax *PAddex [-BM] *PAddex [-BM] *PAddex [-BCM] -W *PAddex [-BM] -W Exercise the data bus at a given address Syntax *PDatex [-BCM] *PDatex [-BCM] *PDatex [-BCM] *PDatex [-BM] Use This command is intended to generate various cycling patterns to assist in debugging address decodes, memory failures etc.
Service Manual Display/debug interface *PMonitor The display/debug interface connects to machines with an external test connector through a 0.025 in sq 0.1 inch pitch 6-way plug. This has connections as follows: Display the text normally written to the LCD. Syntax *PMonitor Use This command may be used to simulate a display adapter using the external test interface.
Service Manual Input Four pulses are sent: the fourth pulse is repeated until ROMCS is asserted in response. The following eight pulses then clock in eight data bits, most significant bit first. ROMCS asserted (overdriven to disable the ROM) is interpreted as a logical '1'. If pulses continue without a break, they should be interpreted as further polling for input and more data may be transferred without returning to the initial four-pulse start-up.
Service Manual Write command Options: Byte operation Word operation 00001xx1 00001xx0 Increment address at each operation 00001x1x Repeat operation at same address 00001X0X Accept new data for each operation 000011XX Use same data for each operation 000010XX Data transfer (all 32-bit words): Operation count (bytes or words to write) Initial address Data Additional data if option bit 2 is set Checksum fixup Note that byte data is sent as words, with only the lower 8 bits significant.
Service Manual Option 110 loop STMIA LDMIA STMIA LDMIA ADDS BCS Option 111 loop STMIA STRB STR LDMIA LDRB LDR ADDS BCS r9,{r11,r12};write and read multiple r9,{r1,r2 ;words r10{r11,r12 r10,{r1,r2} r8, r8, r7 loop r9,{r11,r1 2} ;store multiple words r11,[r10] ;write byte r12,[r9] ;write words r9,{r1,r2} r1,[r10] r1,[r9] ;read single and r8, r8, r7 ;multiple words loop Note that R7 holds the value -1, and is used to decrement the loop counter in R8.
Service Manual Probe_Write Probe_Read (SWI &C8001) (SWI &C8002) Write memory locations in the target machine On entry R0 = target address R1 = block size, in bytes R2 = source address (local machine) R4 = options Read memory locations in the target machine On entry R0 = target address R1 = block size (in bytes) R2 = destination address (local machine) R4 = options On exit R0 = result status Interrupts Interrupts may be enabled Processor mode SVC mode Re-entrancy Not re-entrant On exit R0 = result st
Service Manual Probe_Run Probe_Busex (SWI &C8003) (SWI &C8004) Execute code in the target machine Generate repetitive bus cycles On entry R0 = options R1 = repetition cycles R2 = first address R3 second address R4 = first data R5 = second data On entry R0 = target address On exit R0 = result status Interrupts May be enabled Processor mode SVC mode Re-entrancy Not re-entrant Use To execute built-in ROM self-test function or code previously downloaded using Probe_Write.
Service Manual Probe_Poll Probe_GetWord (SWI &C8005) (SWI &C8006) Read status of interface hardware On entry N/A Read a 32-bit word from the interface hardware On entry R0 = target address On exit R0 = result status R1 = word read Interrupts May be enabled Processor mode SVC mode Re-entrancy Not re-entrant On exit R0 = result status R1 = interface status Flags ST_TXRDY (&10) and ST_RXRDY (&40) in R1 indicate data available from the target and target ready to receive data respectively.
Service Manual Probe_PutWord Probe_GetByte (SWI &C8007) (SWI &C8008) Write a 32-bit word to the interface hardware On entry R1 = word to write Read a 8-bit byte from the interface hardware On exit R0 = result status Interrupts May be enabled Processor mode SVC mode Re-entrancy Not re-entrant Use To perform low-level operations required to transfer data for the SWIs &C8000 to &C8004.
Service Manual Probe_PutByte Probe_GetSlow (SWI &C8009) (SWI &C800A) Read a byte slowly from the interface hardware On entry R0 target address On exit R0 = result status R1 = byte read Interrupts May be enabled Processor mode SVC mode Re-entrancy Not re-entrant Use To read data normally intended for the LCD module. This SWI is similar to Probe_GetByte, but ensures that the data remains latched on the interface sufficiently long to permit the LCD module to accept the data.
Service Manual Repairing a 'dead' computer See the section entitled Checking a 'dead' computer on page 4-2 for initial tests. These notes are a guide to diagnosing and repairing faults on the main PCB, resulting from the initial tests. Video failure 1 Check for +5 Von both ends of L1; if open circuit then check C9 for short circuit. Also check for 3.5 Volts ( approx.) on IC 54 pin 43. Should this not be present then check R10, D4 and C31. 2 Check for a 24 MHz clock on IC54 pin 19.
Service Manual Note the correct position of the ROMs in their sockets; ROM pin 1 is two rows down from the 'top' of the socket. Fitting the test ROMs in place of the RISC OS ROMs Providing that the ARM, memory controller and video controller are functioning, the test ROMs will auto-boot into the menu-driven display shown in Fig 5-4 Test ROM display menu. At any point in the operation of the test ROMs, pressing the BREAK key or re-powering the machine will re-start the program and re-display the menu.
Service Manual sequence 0123456789 is repeated across the top line of the display. Every 4 digits represents a 32 bit word. Watch for missing or corrupted display. After setting the border colour to white, the signals should be observable in the following order. As the start of the screen memory is known to be at physical address &2000000, it should be possible to determine the exact device that is faulty by examining the corruption pattern on the display.
Service Manual After execution of this code, the border colour is reset to black. The assembler listing for this section of code is shown below: Start1 5-26 LDRT r0, [r5] ;SVPMD pin low) LDRT r0, [r5] ; )continual toggle of:- LDRT r0, [r5] ; ) LDR r1, iocmof ;re-load ioc base addr.
Service Manual Repairs following functional testing Monitor Screen The following notes refer to the functional test procedures described in the previous chapter, and give component level diagnosis and repair information following a test failure. Unless otherwise stated, always perform the simple checks given in Part 4 - Fault diagnosis first, then refer to the relevant component level information below.
Service Manual Keyboard and mouse Check computer interface by swapping to a known good keyboard and mouse. If failure still present, check continuity of keyboard connector SK 11 and ensure that +5 V can be found on pin 4 and 0 V on pin 3. Check functionality of inverting buffers in IC 3, check continuity through R 62 and R 101. Check REF8M clock at IC58 pin 8 with a digital frequency meter. Replace IOC IC 58.
Service Manual Part 6 - Parts lists The parts lists in this chapter detail the components used in the manufacture of workstations and upgrades. The parts lists are given under the following headings: • Main PCB • 4MB RAM upgrade card • Backplane • ARMS daughter card (PGA) • Keyboard and adaptor card (membrane keyboard) or Keyboard assembly (keyswitch keyboard) • Ethernet I card or Ethernet II card • SCSI interface card. There is a circuit diagram for each of the above items.
Service Manual Item C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 0124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 6-2 Description CPCTR 2N2 CPLT 30V 10% 5P CPCTR 33P CPLT 30V 2% CPCTR 470P CPLT 30V 10% CPCTR 100P CPLT 30V 2% CPCTR 100P C
Service Manual Item IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 IC15 IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC23 IC24 IC25 IC26 IC27 IC28 IC29 IC30 IC31 IC32 IC33 IC34 IC35 IC36 IC37 IC38 IC39 IC40 IC41 IC42 IC43 IC44 IC45 IC46 IC47 IC48 IC49 IC50 IC51 IC52 IC53 IC54 IC55 IC56 IC57 IC58 IC59 IC60 IC61 IC62 IC63 IC64 IC65 IC66 IC67 IC68 IC69 IC70 IC71 IC72 IC73 IC74 IC75 IC76 IC77 IC78 IC79 IC80 L1 L2 L3 L4 L5 L6 L7 L8 L9 Description IC 74ACT245 CMOS 20/0.3" IC 74ACT153 CMOS 16/0.3" IC 74HCT573 CMOS 20/0.
Service Manual Item R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 6-4 Description RES 33R SMD 5% 0W25 1206 RES 1K0 SMD 5% 0W25 1206 RES 180R SMD 5% 0W25 1206 RES 100K SMD 5% 0W25 1206 RES 100R SMD 5% 0W25 120
Service Manual Item R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 Description RES 4K7 SMD 5% 0W25 1206 RES 68R SMD 5% 0W25 1206 RES 68R SMD
Service Manual 4MB RAM card (optional upgrade) Item 1 2 3 15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 ICI IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 L1 L2 L3 PL1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 6-6 Description BARE PCB PCB ASSEMBLY DRG PCB CIRCUIT DIAGRAM LABEL SERIAL PCB CPCTR 47U TANT SMD CPCTR 47U TANT SMD CPCTR 47U TANT SMD CPCTR 47U TANT SMD CPCTR 33N DCPLR SMD1210 CPCTR 33N DCPLR
Service Manual Keyboard adaptor PCB ( membrane keyboard) ARMS (PGA) Daughter card Item Description Qty Item 1 2 3 15 C1 C2 C3 C4 C5 C6 C7 IC1 IC2 R1 R2 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 SK1 BARE PCB PCB ASSEMBLY DRG PCB CIRCUIT DIAGRAM LABEL SERIAL PCB CPCTR 47U ALEC 10V AX CPCTR 47U AL
Service Manual Ethernet I Keyboard adaptor PCB (cont) (membrane keyboard) Item SK2 SK3 SW1 X1 Description Qty CONR 20W FLEX PCB CONR 9W SKT M/DIN RA RFI SW 2P MOM CO P/B RA PCB XTAL 12.00MHZ HC18 1 1 1 1 Keyboard assembly (keyswitch keyboard) This is a service replacement item. Part numbers: 0186,012 (keyboard subassembly) 0086,900/A (complete keyboard unit).
Service Manual Ethernet II Item 1 2 3 7 8 11 13 14 15 16 18 19 20 22 23 25 26 28 29 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 RP1 RP2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 IC1 Description Qty BARE PCB ASSEMBLY DRAWING CIRCUIT DIAGRAM ETHERNET II REAR PANEL PCB SUPPORT MOUNTING BRKT CONR 2W SHUNT 0.1" LK3 to 8 SKT IC 20/0.3" SUPA IC10,14,18,19 SKT IC 32/0.
Service Manual SCSI interface card (issue 2+) Item 1 2 3 6 8 10 13 15 16 17 18 21 22 24 25 26 28 R1 R2 R3 R4 R5 R10 R17 R19 R21 R22 R25 Description BARE SCSI PCB {Iss 2+} ASSEMBLY DRAWING CIRCUIT DIAGRAM SCSI PCB BACKPANEL PODULE PCB BRACKET {STD} CONRDL 50W PLG SCSI TERM SK1 CONR 2W SHUNT 0.1" LK4,5,6,7 SKT IC 20/0.3" SUPA IC9,12,14,15,18 SKT IC 32/0.
Service Manual Appendix A - Mouse test jig template You can use the template above as a test jig, but take care that the mouse does not slip on the paper. You can construct a better jig as follows: 1 Using wood or metal strips, construct a test jig with the dimensions shown in the template (plan view) above. 2 Secure the test jig to a firm, flat, horizontal, non-slip surface. 3 Mark out the three button boxes shown on the template.
Service Manual A-2 Issue 2, June 1991 Appendix A - Mouse test jig template
Service Manual Appendix B - Ethernet test feedback leads Pin mappings for Ethernet II and Ethernet I test feedback leads Parts list See over for instructions on constructing the leads.
Service Manual Constructing the test feedback leads One solution is to incorporate the LEDs in the cover of the 15-way D-type plug. This involves modifying the plug's cover, but makes for a neat, compact test lead with no unnecessary trailing wires. The finished lead should look like that shown in the figure below.
Service Manual Appendix C - Serial port loopback plug* Item Part no.
Service Manual C-2 Issue 2, June 1991 Appendix C - Serial port loopback plug
Service Manual Appendix D - Earth continuity testing Equipment required DANGER THE FOLLOWING TESTS INVOLVE HIGH CURRENTS BUT LOW VOLTAGES. ALL NECESSARY PRECAUTIONS MUST BE TAKEN TO ENSURE OPERATOR SAFETY DURING TESTING. An earth continuity tester capable of sourcing 25A derived from an AC source with a no-load voltage not exceeding 12V. It is recommended that the calibration and operation of the instrument be checked frequently enough to ensure its accuracy.
Service Manual D-2 Issue 2, June 1991 Appendix D - Earth continuity testing
Service Manual Appendix E - DC insulation testing - class 1 UK information only Before testing Equipment required Check the mains lead and plug for any physical damage and replace if necessary. A portable appliance tester or an insulation tester that provides 500V DC ONLY. Note that the computer contains RFI capacitors on the PSU input. It is recommended that the calibration and operation of the instrument be checked frequently enough to ensure its accuracy.
Service Manual E-2 Issue 2, June 1991 Appendix E - DC insulation testing - class 1
