User`s manual

2.3.15 LVDS Connector (LVDS2)
Description PIN No. PIN No. Description
+5V 2 1 +3.3V
+5V 4 3 +3.3V
Ground 6 5 Ground
LCTLB_CLK_L 8 7 LDDC_CLKL
LCTLB_DATA_L 10 9 LDDC_DATA_L
Ground 12 11 Ground
Ground 14 13 Ground
A_CLK- 16 15 B_CLK-
A_CLK+ 18 17 B_CLK+
Ground 20 19 Ground
A_DATA0- 22 21 B_DATA0-
A_DATA0+ 24 23 B_DATA0+
Ground 26 25 Ground
A_DATA1- 28 27 B_DATA1-
A_DATAP+ 30 29 B_DATA1+
Ground 32 31 Ground
A_DATA2- 34 33 B_DATA2-
A_DATA2+ 36 35 B_DATA2+
Ground 38 37 Ground
+12V 40 39 +12V
Signal Type Description
LCTLB_CLK_L I/O I
2
C Based control signal (Clock) for External SSC clock chip control
LCTLB_DATAL I/O I
2
C Based control signal (Data) for External SSC clock chip control
LDDC_CLKL I/O EDID support for flat panel display
LDDC_DATAL I/O EDID support for flat panel display