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Revision: 1.0

3.4.3 I/O-Interface Address Map

The following table shows the I/O Address map, including descriptions and their offset

addresses relative to the “PCI Base Address1”.

ACE-B2019/A I/O Address map

32 bit Register

I/O Offset

Address

31 24 23 16 15 8 7 0

Software

Readabl

Software

Writable

00h Reserved

SRAM operation

mode

Yes Ye s

04h Reserved DIP Switch Yes N o

08h Reserved Interrupt & Timer Enable Register Yes Yes

0Ch Reserved I/O & Timer Interrupt Source Registers Yes No

10h Reserved Port BCD Mode Yes Yes

14h Reserved Port A Data Yes Yes

18h Reserved Port B Data Yes Yes

1Ch Reserved Port C Data Yes Yes

20h Reserved Port D Data Yes Yes

24h Reserved Port EFGH Mode Yes Yes

28h Reserved Port E Data Yes Yes

2Ch Reserved Port F Data Yes Yes

30h Reserved Port G Data Yes Yes

34h Reserved Port H Data Yes Yes

38h Reserved Port IJKL Mode Yes Yes

3Ch Reserved Port I Data Yes Yes

40h Reserved Port J Data Yes Yes

44h Reserved Port K Data Yes Yes

48h Reserved Port L Data Yes Yes

4Ch TIMER-A Register Yes Yes

50h TIMER-B Register Yes Yes

54h TIMER-C Register Yes Yes

58h TIMER-D Register Yes Yes

5Ch Timer Resolution Yes Yes

60h Port D de-bounce Port C de-bounce Port B de-bounce Port A de-bounce Yes Yes

64h Port H de-bounce Port G de-bounce Port F de-bounce Port E de-bounce Yes Yes

68h Port L de-bounce Port K de-bounce Port J de-bounce Port I de-bounce Yes Yes

6Ch

70h Reserved REEL Interrupt REEL Enable

REEL Function

Enable

80h REEL A Lamp REEL A Feedback Pattern REEL A Status

84h REEL A Running Steps REEL A Timing

88h Reserved REEL A Steps

8Ch Reserved

90h REEL B Lamp REEL B Feedback Pattern REEL B Status

94h REEL B Running Steps Motor B Timing