Datasheet
Equivalent
Circuit
f =250kHz
CLK
Z
CM
Z
DIFF
Z
CM
AIN
N
AIN
P
0.7V
0.7V
S
1
S
1
C
A1
C
B
C
A2
S
2
S
2
0.7V
0.7V
AIN
N
AIN
P
ADS1113
ADS1114
ADS1115
www.ti.com
SBAS444B –MAY 2009–REVISED OCTOBER 2009
Figure 26. Simplified Analog Input Circuit
The common-mode input impedance is measured by The typical value of the input impedance cannot be
applying a common-mode signal to shorted AIN
P
and neglected. Unless the input source has a low
AIN
N
inputs and measuring the average current impedance, the ADS1113/4/5 input impedance may
consumed by each pin. The common-mode input affect the measurement accuracy. For sources with
impedance changes depending on the PGA gain high output impedance, buffering may be necessary.
setting, but is approximately 6MΩ for the default PGA Active buffers introduce noise, and also introduce
gain setting. In Figure 26, the common-mode input offset and gain errors. All of these factors should be
impedance is Z
CM
. considered in high-accuracy applications.
The differential input impedance is measured by Because the clock oscillator frequency drifts slightly
applying a differential signal to AIN
P
and AIN
N
inputs with temperature, the input impedances also drift. For
where one input is held at 0.7V. The current that many applications, this input impedance drift can be
flows through the pin connected to 0.7V is the ignored, and the values given in Table 2 for typical
differential current and scales with the PGA gain input impedance are valid.
setting. In Figure 26, the differential input impedance
is Z
DIFF
. Table 2 describes the typical differential input
FULL-SCALE INPUT
impedance.
A programmable gain amplifier (PGA) is implemented
before the ΔΣ core of the ADS1114/5. The PGA can
Table 2. Differential Input Impedance
be set to gains of 2/3, 1, 2, 4, 8, and 16. Table 3
FS (V) DIFFERENTIAL INPUT IMPEDANCE
shows the corresponding full-scale (FS) ranges. The
±6.144V
(1)
22MΩ
PGA is configured by three bits in the Config register.
The ADS1113 has a fixed full-scale input range of
±4.096V
(1)
15MΩ
±2.048V. The PGA = 2/3 setting allows input
±2.048V 4.9MΩ
measurement to extend up to the supply voltage
±1.024V 2.4MΩ
when VDD is larger than 4V. Note though that in this
±0.512V 710kΩ
case (as well as for PGA = 1 and VDD < 4V), it is not
±0.256V 710kΩ
possible to reach a full-scale output code on the
ADC. Analog input voltages may never exceed the
1. This parameter expresses the full-scale range of
analog input voltage limits given in the Electrical
the ADC scaling. In no event should more than
Characteristics table.
VDD + 0.3V be applied to this device.
Table 3. PGA Gain Full-Scale Range
PGA SETTING FS (V)
2/3 ±6.144V
(1)
1 ±4.096V
(1)
2 ±2.048V
4 ±1.024V
8 ±0.512V
16 ±0.256V
1. This parameter expresses the full-scale range of
the ADC scaling. In no event should more than
VDD + 0.3V be applied to this device.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS1113 ADS1114 ADS1115