Datasheet

0x7FFF
OutputCode
-FS
¼
0
¼
FS
InputVoltage(AIN AIN )-
P N
0x7FFE
0x0001
¼
0x0000
0x8000
0xFFFF
0x8001
¼
-FS
2 - 1
15
2
15
FS
2 - 1
15
2
15
ADS1113
ADS1114
ADS1115
SBAS444B –MAY 2009–REVISED OCTOBER 2009 www.ti.com
DATA FORMAT The ADS1113/4/5 digital filter provides some
attenuation of high-frequency noise, but the digital
The ADS1113/4/5 provide 16 bits of data in binary
Sinc filter frequency response cannot completely
twos complement format. The positive full-scale input
replace an anti-aliasing filter. For a few applications,
produces an output code of 7FFFh and the negative
some external filtering may be needed; in such
full-scale input produces an output code of 8000h.
instances, a simple RC filter is adequate.
The output clips at these codes for signals that
exceed full-scale. Table 4 summarizes the ideal When designing an input filter circuit, be sure to take
output codes for different input signals. Figure 27 into account the interaction between the filter network
shows code transitions versus input voltage. and the input impedance of the ADS1113/4/5.
Table 4. Input Signal versus Ideal Output Code
OPERATING MODES
INPUT SIGNAL, V
IN
The ADS1113/4/5 operate in one of two modes:
(AIN
P
– AIN
N
) IDEAL OUTPUT CODE
(1)
continuous conversion or single-shot. In continuous
≥ FS (2
15
– 1)/2
15
7FFFh
conversion mode, the ADS1113/4/5 continuously
+FS/2
15
0001h
perform conversions. Once a conversion has been
completed, the ADS1113/4/5 place the result in the
0 0
Conversion register and immediately begins another
–FS/2
15
FFFFh
conversion. In single-shot mode, the ADS1113/4/5
≤ –FS 8000h
wait until the OS bit is set high. Once asserted, the bit
is set to '0', indicating that a conversion is currently in
1. Excludes the effects of noise, INL, offset, and
progress. Once conversion data are ready, the OS bit
gain errors.
reasserts and the device powers down. Writing a '1'
to the OS bit during a conversion has no effect.
RESET AND POWER-UP
When the ADS1113/4/5 powers up, a reset is
performed. As part of the reset process, the
ADS1113/4/5 set all of the bits in the Config register
to the respective default settings.
The ADS1113/4/5 respond to the I
2
C general call
reset command. When the ADS1113/4/5 receive a
general call reset, an internal reset is performed as if
the device had been powered on.
DUTY CYCLING FOR LOW POWER
For many applications, the improved performance at
low data rates may not be required. For these
applications, the ADS1113/4/5 support duty cycling
Figure 27. ADS1113/4/5 Code Transition Diagram
that can yield significant power savings by
periodically requesting high data rate readings at an
effectively lower data rate. For example, an
ALIASING
ADS1113/4/5 in power-down mode with a data rate
As with any data converter, if the input signal
set to 860SPS could be operated by a microcontroller
contains frequencies greater than half the data rate,
that instructs a single-shot conversion every 125ms
aliasing occurs. To prevent aliasing, the input signal
(8SPS). Because a conversion at 860SPS only
must be bandlimited. Some signals are inherently
requires about 1.2ms, the ADS1113/4/5 enter
bandlimited. For example, the output of a
power-down mode for the remaining 123.8ms. In this
thermocouple, which has a limited rate of change.
configuration, the ADS1113/4/5 consume about
Nevertheless, they can contain noise and interference
1/100th the power of the ADS1113/4/5 operated in
components. These components can fold back into
continuous conversion mode. The rate of duty cycling
the sampling band in the same way as with any other
is completely arbitrary and is defined by the master
signal.
controller. The ADS1113/4/5 offer lower data rates
that do not implement duty cycling and offer improved
noise performance if it is needed.
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