Datasheet

ADS1113
ADS1114
ADS1115
SBAS444B –MAY 2009–REVISED OCTOBER 2009 www.ti.com
When reading from the ADS1113/4/5, the previous POINTER REGISTER
value written to the Pointer register determines the
The four registers are accessed by writing to the
register that is read from. To change which register is
Pointer register byte; see Figure 30. Table 6 and
read, a new value must be written to the Pointer
Table 7 indicate the Pointer register byte map.
register. To write a new value to the Pointer register,
the master issues a slave address byte with the R/W
Table 6. Register Address
bit low, followed by the Pointer register byte. No
BIT 1 BIT 0 REGISTER
additional data need to be transmitted, and a STOP
condition can be issued by the master. The master
0 0 Conversion register
may now issue a START condition and send the
0 1 Config register
slave address byte with the R/W bit high to begin the
1 0 Lo_thresh register
read. Table 10 details this sequence. If repeated
1 1 Hi_thresh register
reads from the same register are desired, there is no
need to continually send Pointer register bytes,
because the ADS1113/4/5 store the value of the
CONVERSION REGISTER
Pointer register until it is modified by a write
The 16-bit register contains the result of the last
operation. However, every write operation requires
conversion in binary twos complement format.
the Pointer register to be written.
Following reset or power-up, the Conversion register
is cleared to '0', and remains '0' until the first
REGISTERS
conversion is completed.
The ADS1113/4/5 have four registers that are
The register format is shown in Table 8.
accessible via the I
2
C port. The Conversion register
contains the result of the last conversion. The Config
CONFIG REGISTER
register allows the user to change the ADS1113/4/5
operating modes and query the status of the devices.
The 16-bit register can be used to control the
Two registers, Lo_thresh and Hi_thresh, set the
ADS1113/4/5 operating mode, input selection, data
threshold values used for the comparator function.
rate, PGA settings, and comparator modes. The
register format is shown in Table 9.
Table 7. Pointer Register Byte (Write-Only)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 0 0 Register address
Table 8. Conversion Register (Read-Only)
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 9. Config Register (Read/Write)
BIT 15 14 13 12 11 10 9 8
NAME OS MUX2 MUX1 MUX0 PGA2 PGA1 PGA0 MODE
blank
BIT 7 6 5 4 3 2 1 0
NAME DR2 DR1 DR0 COMP_MODE COMP_POL COMP_LAT COMP_QUE1 COMP_QUE0
Default = 8583h.
Bit [15] OS: Operational status/single-shot conversion start
This bit determines the operational status of the device.
This bit can only be written when in power-down mode.
For a write status:
0 : No effect
1 : Begin a single conversion (when in power-down mode)
For a read status:
0 : Device is currently performing a conversion
1 : Device is not currently performing a conversion
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