Datasheet

Module specifications LSM303DLHC
12/42 Doc ID 018771 Rev 1
2.4 Communication interfaces characteristics
External pull-up resistors are required to support I
2
C standard and fast speed modes.
2.4.1 Sensor I
2
C - inter IC control interface
Subject to general operating conditions for Vdd and Top.
Figure 3. I
2
C slave timing diagram
(c)
Table 6. I
2
C slave timing values
Symbol Parameter
I
2
C standard mode
(1)
I
2
C fast mode
(1)
Unit
Min. Max. Min. Max.
f
(SCL)
SCL clock frequency 0 100 0 400 KHz
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100 ns
t
h(SDA)
SDA data hold time 0.01 3.45 0.01 0.9 µs
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000
20 + 0.1C
b
(2)
300
ns
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300
20 + 0.1C
b
(2)
300
t
h(ST)
START condition hold time 4 0.6
µs
t
su(SR)
Repeated START condition
setup time
4.7 0.6
t
su(SP)
STOP condition setup time 4 0.6
t
w(SP:SR)
Bus free time between STOP
and START condition
4.7 1.3
1. Data based on standard I
2
C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
SDA
SCL
t
f(SDA)
t
su(SP)
t
w(SCLL)
t
su(SDA)
t
r(SDA)
t
su(SR)
t
h(ST)
t
w(SCLH)
t
h(SDA)
t
r(SCL)
t
f(SCL)
t
w(SP:SR)
START
REPEATED
START
STOP
START
AM09238V1