Datasheet

Register mapping LSM303DLHC
22/42 Doc ID 018771 Rev 1
6 Register mapping
Table 17 provides a listing of the 8-bit registers embedded in the device and the related
addresses:
Table 17. Register address map
Name
Slave
address
Type
Register address
Default Comment
Hex Binary
Reserved (do not modify) Table 14 00 - 1F -- -- Reserved
CTRL_REG1_A Table 14 rw 20 010 0000 00000111
CTRL_REG2_A Table 14 rw 21 010 0001 00000000
CTRL_REG3_A Table 14 rw 22 010 0010 00000000
CTRL_REG4_A Table 14 rw 23 010 0011 00000000
CTRL_REG5_A Table 14 rw 24 010 0100 00000000
CTRL_REG6_A Table 14 rw 25 010 0101 00000000
REFERENCE_A Table 14 rw 26 010 0110 00000000
STATUS_REG_A Table 14 r 27 010 0111 00000000
OUT_X_L_A Table 14 r 28 010 1000 output
OUT_X_H_A Table 14 r 29 010 1001 output
OUT_Y_L_A Table 14 r 2A 010 1010 output
OUT_Y_H_A Table 14 r 2B 010 1011 output
OUT_Z_L_A Table 14 r 2C 010 1100 output
OUT_Z_H_A Table 14 r 2D 010 1101 output
FIFO_CTRL_REG_A Table 14 rw 2E 010 1110 00000000
FIFO_SRC_REG_A Table 14 r 2F 010 1111
INT1_CFG_A Table 14 rw 30 011 0000 00000000
INT1_SOURCE_A Table 14 r 31 011 0001 00000000
INT1_THS_A Table 14 rw 32 011 0010 00000000
INT1_DURATION_A Table 14 rw 33 011 0011 00000000
INT2_CFG_A Table 14 rw 34 011 0100 00000000
INT2_SOURCE_A Table 14 r 35 011 0101 00000000
INT2_THS_A Table 14 rw 36 011 0110 00000000
INT2_DURATION_A Table 14 rw 37 011 0111 00000000
CLICK_CFG_A Table 14 rw 38 011 1000 00000000
CLICK_SRC_A Table 14 rw 39 011 1001 00000000
CLICK_THS_A Table 14 rw 3A 011 1010 00000000
TIME_LIMIT_A Table 14 rw 3B 011 1011 00000000