Datasheet

24/42 Doc ID 018771 Rev 1

7 Register description

The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The register address, made up of 7 bits, is used to identify them and to

write the data through the serial interface.

7.1 Linear acceleration register description

7.1.1 CTRL_REG1_A (20h)

ODR<3:0> is used to set the power mode and ODR selection. In Table 20 all frequencies

resulting in a combination of ODR<3:0> are listed.

Table 18. CTRL_REG1_A register

ODR3 ODR2 ODR1 ODR0 LPen Zen Yen Xen

Table 19. CTRL_REG1_A description

ODR3-0

Data rate selection. Default value: 0

(0000: power-down, others: refer to Table 20.)

LPen

Low-power mode enable. Default value: 0

(0: normal mode, 1: low-power mode)

Zen

Z axis enable. Default value: 1

(0: Z axis disabled, 1: Z axis enabled)

Ye n

Y axis enable. Default value: 1

(0: Y axis disabled, 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled, 1: X axis enabled)

Table 20. Data rate configuration

ODR3 ODR2 ODR1 ODR0 Power mode selection

0000Power-down mode

0 0 0 1 Normal / low-power mode (1 Hz)

0 0 1 0 Normal / low-power mode (10 Hz)

0 0 1 1 Normal / low-power mode (25 Hz)

0 1 0 0 Normal / low-power mode (50 Hz)

0 1 0 1 Normal / low-power mode (100 Hz)

0 1 1 0 Normal / low-power mode (200 Hz)

0 1 1 1 Normal / low-power mode (400 Hz)