Datasheet

LSM303DLHC Register description
Doc ID 018771 Rev 1 25/42
7.1.2 CTRL_REG2_A (21h)
7.1.3 CTRL_REG3_A (22h)
1000Low-power mode (1.620 KHz)
1 0 0 1 Normal (1.344 kHz) / low-power mode (5.376 KHz)
Table 20. Data rate configuration (continued)
ODR3 ODR2 ODR1 ODR0 Power mode selection
Table 21. CTRL_REG2_A register
HPM1 HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1
Table 22. CTRL_REG2_A description
HPM1 -HPM0 High pass filter mode selection. Default value: 00
(refer to Table 23)
HPCF2 -
HPCF1
High pass filter cut-off frequency selection
FDS
Filtered data selection. Default value: 0
(0: internal filter bypassed, 1: data from internal filter sent to output register and
FIFO)
HPCLICK
High pass filter enabled for CLICK function.
(0: filter bypassed, 1: filter enabled)
HPIS2 High pass filter enabled for AOI function on Interrupt 2,
(0: filter bypassed, 1: filter enabled)
HPIS1 High pass filter enabled for AOI function on Interrupt 1,
(0: filter bypassed, 1: filter enabled)
Table 23. High pass filter mode configuration
HPM1 HPM0 High pass filter mode
0 0 Normal mode (reset reading HP_RESET_FILTER)
0 1 Reference signal for filtering
1 0 Normal mode
1 1 Autoreset on interrupt event
Table 24. CTRL_REG3_A register
I1_CLICK I1_AOI1 I1_AOI2 I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN --