Datasheet

LSM303DLHC Register description
Doc ID 018771 Rev 1 27/42
7.1.6 CTRL_REG6_A (25h)
7.1.7 REFERENCE/DATACAPTURE_A (26h)
Table 29. CTRL_REG5_A description
BOOT Reboot memory content. Default value: 0
(0: normal mode, 1: reboot memory content)
FIFO_EN FIFO enable. Default value: 0
(0: FIFO disable, 1: FIFO enable)
LIR_INT1 Latch interrupt request on INT1_SRC register, with INT1_SRC register
cleared by reading INT1_SRC itself. Default value: 0.
(0: interrupt request not latched, 1: interrupt request latched)
D4D_INT1 4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set
to 1.
LIR_INT2 Latch interrupt request on INT2_SRC register, with INT2_SRC register
cleared by reading INT2_SRC itself. Default value: 0.
(0: interrupt request not latched, 1: interrupt request latched)
D4D_INT2 4D enable: 4D detection is enabled on INT2 when 6D bit on INT2_CFG is set
to 1.
Table 30. CTRL_REG6_A register
I2_CLICKen I2_INT1 I2_INT2 BOOT_I1 P2_ACT - - H_LACTIVE --
Table 31. CTRL_REG6_A description
I2_CLICKen CLICK interrupt on PAD2. Default value 0.
(0: disable, 1: enable)
I2_INT1 Interrupt 1 on PAD2. Default value 0.
(0: disable, 1: enable)
I2_INT2 Interrupt 2 on PAD2. Default value 0.
(0: disable, 1: enable)
BOOT_I1 Reboot memory content on PAD2. Default value: 0
(0: disable, 1: enable)
P2_ACT Active function status on PAD2. Default value 0.
(0: disable, 1: enable)
H_LACTIVE Interrupt active high, low. Default value 0.
(0: active high, 1: active low)
Table 32. REFERENCE_A register
Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0