Datasheet

LSM303DLHC Register description
Doc ID 018771 Rev 1 31/42
Interrupt 1 source register. Read only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refreshing of data in the INT1_SRC register if the latched option was
chosen.
7.1.16 INT1_THS_A (32h)
7.1.17 INT1_DURATION_A (33h)
D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
7.1.18 INT2_CFG_A (34h)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Table 44. INT1_SRC_A description (continued)
Table 45. INT1_THS_A register
0
(1)
1. This bit must be set to ‘0’ for correct working of the device.
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 46. INT1_THS_A description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
Table 47. INT1_DURATION_A register
0
(1)
1. This bit must be set to ‘0’ for correct working of the device.
D6 D5 D4 D3 D2 D1 D0
Table 48. INT1_DURATION_A description
D6 - D0 Duration value. Default value: 000 0000
Table 49. INT2_CFG_A register
AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE