Datasheet

LSM303DLHC Register description
Doc ID 018771 Rev 1 33/42
Interrupt 2 source register. Read only register.
Reading at this address clears INT2_SRC IA bit (and the interrupt signal on the INT 2 pin)
and allows the refreshing of data in the INT2_SRC register if the latched option was chosen.
7.1.20 INT2_THS_A (36h)
7.1.21 INT2_DURATION_A (37h)
Table 53. INT2_SRC_A description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated, 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt, 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X Low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Table 54. INT2_THS_A register
0
(1)
1. This bit must be set to ‘0’ for correct working of the device
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 55. INT2_THS_A description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
Table 56. INT2_DURATION_A register
0
(1)
1. This bit must be set to ‘0’ for correct working of the device
D6 D5 D4 D3 D2 D1 D0
Table 57. INT2_DURATION_A description
D6-D0 Duration value. Default value: 000 0000