Datasheet
21
9596A–AT42–10/10
AT42QT1070
5.8 Address 32 – 38: Negative Threshold (NTHR)
NTHR Keys 0 – 6: these 8-bit values set the threshold value for each key to register a detection.
Default: 20 counts
Note: Do not use a setting of 0 as this causes a key to go into detection when its signal is
equal to its reference.
5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS)
AVE 0–5: The Averaging Factor (AVE) is the number of pulses which are added together and
averaged to get the final signal value for that channel.
For example, if AVE = 8 then 8 ADC samples are taken and added together. The result is
divided by the original number of pulses (8). If sixteen pulses are used then the result is divided
by sixteen.
This provides a better signal-to-noise ratio but requires longer acquire times. Values for AVE are
restricted internally to 1, 2, 4, 8, 16 or 32.
Default: 8 (In standalone mode key 0 is 16)
AKS 0–1: these bits control which keys are included in an AKS group. There can be up to three
groups, each containing any number of keys (up to the maximum allowed for the mode).
Each key can have a value between 0 and 3, which assigns it to an AKS group of that number. A
key may only go into detect when it has the largest signal change of any key in its group. A value
of 0 means the key is not in any AKS group.
Default: 0x01
5.10 Address 46 – 52: Detection Integrator (DI)
DETECTION INTEGRATOR: addresses 46 – 52 allow the DI level to be set for each key. This
8-bit value controls the number of consecutive measurements that must be confirmed as having
passed the key threshold before that key is registered as being in detect. The minimum value for
the DI filter is 2. Settings of 0 and 1 for the DI also default to 2 because a minimum of two
consecutive measurements must be confirmed.
Default: 4
Table 5-8. NTHR
Address b7 b6 b5 b4 b3 b2 b1 b0
32 – 38 NEGATIVE THRESHOLD FOR KEYS 0 – 6
Table 5-9. AVE/AKS
Address b7 b6 b5 b4 b3 b2 b1 b0
39 – 45 AVE5 AVE4 AVE3 AVE2 AVE1 AVE0 AKS1 AKS0
Table 5-10. Detection Integrator
Address b7 b6 b5 b4 b3 b2 b1 b0
46 – 52 DETECTION INTEGRATOR