Datasheet

31
9596A–AT42–10/10
AT42QT1070
Appendix A. I
2
C-compatible Operation
A.1 Interface Bus
The device communicates with the host over an I
2
C-compatible bus. The following sections give
an overview of the bus; more detailed information is available from www.i2C-bus.org. Devices
are connected to the I
2
C-compatible bus as shown in Figure A-1. Both bus lines are connected
to Vdd via pull-up resistors. The bus drivers of all I
2
C-compatible devices must be open-drain
type. This implements a wired “AND” function that allows any and all devices to drive the bus,
one at a time. A low level on the bus is generated when a device outputs a zero.
Figure A-1. I
2
C-compatible Interface Bus
A.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; the only exception to this rule is for
generating START and STOP conditions.
Figure A-2. Data Transfer
A.3 START and STOP Conditions
The host initiates and terminates a data transmission. The transmission is initiated when the
host issues a START condition on the bus, and is terminated when the host issues a STOP
condition. Between the START and STOP conditions, the bus is considered busy. As shown in
Figure A-3, START and STOP conditions are signaled by changing the level of the SDA line
when the SCL line is high.
Vdd
Device 1 Device 2 Device 3 Device n R1 R2
SDA
SCL
SDA
SCL
Data Stable Data Stable
Data Change